Level-Shift Circuit With Fixed Intermediate Nodes for 50% Duty Ratio
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Solution Overview
Problem
Level-shift circuits with a tolerant structure face challenges in achieving high-speed signal transmission due to delays in state transitions and an uneven duty ratio, primarily caused by the use of MOS transistors with a stack configuration that results in intermediate nodes becoming high impedance, leading to fluctuating delay periods and pulse width variations.
Innovation Solution
A semiconductor integrated circuit design that stabilizes the voltage of intermediate nodes using a switch circuit and synthesizes differential outputs to improve the duty ratio, ensuring consistent delay periods and enabling high-speed signal transmission by configuring additional transistors as switch circuits and employing a synthesis circuit to balance rising and falling transition delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If MOS transistors with a stack configuration are used to implement a tolerant structure, then the circuit can prevent voltage exceeding withstand voltages from being applied to elements, but the state transition of the output node is delayed and the duty ratio does not reach 50%
Solution Approach 1:
The patent divides the tolerant structure into separate segments: the stack configuration transistors (M1, M2) remain for voltage protection, while additional transistors (M3, M4) are introduced as dedicated switching elements. This segmentation allows the protective function to be separated from the switching function, enabling faster state transitions without compromising voltage protection capability.
Solution Approach 2:
The patent introduces intermediate switching transistors (M3, M4) that act as mediators between the input signal and the output node. These intermediary elements accelerate the state transition by providing dedicated switching paths, while the original stack transistors (M1, M2) continue to provide voltage protection without being the bottleneck for speed.
2Reliability
If MOS transistors with a stack configuration are used to implement a tolerant structure, then the circuit can prevent voltage exceeding withstand voltages from being applied to elements, but the duty ratio of output does not reach 50%
Solution Approach 1:
The patent segments the circuit functions by separating the voltage protection role (stack transistors M1, M2) from the duty ratio control role (switching transistors M3, M4). This allows independent optimization of each function, enabling precise control of the duty ratio to achieve 50% while maintaining voltage protection capability.
Solution Approach 2:
The patent employs feedback mechanisms where the switching transistors (M3, M4) are controlled based on the state of the stack transistors (M1, M2). This feedback ensures that the duty ratio is precisely regulated to maintain 50% stability, compensating for any variations in the stack configuration's behavior.
3Device complexity
If the voltage of intermediate nodes is not fixed, then the circuit structure remains simple, but the delay period fluctuates and pulse width varies
Solution Approach 1:
The patent applies preliminary action by pre-establishing fixed voltage paths for intermediate nodes through the switching transistors (M3, M4). These transistors proactively control the voltage state of intermediate nodes before signal transitions occur, eliminating delay fluctuations and pulse width variations without requiring complex feedback circuits.
Data Source
AI summary
A semiconductor integrated circuit of embodiments includes a first MOS transistor configured to control conduction and non-conduction between a reference voltage point and a node, a second MOS transistor connected to the first MOS transistor via the node and configured to apply a voltage equal to or lower than a withstand voltage of the first MOS transistor to the node, a third MOS transistor configured to receive supply of a second voltage higher than the first voltage, and output an output signal of a signal level corresponding to a voltage range of the second voltage, and a switch circuit configured to make a voltage of the node a fixed voltage when the first MOS transistor is in an OFF state.