Level Shift Circuit With Push-Pull Buffer for Low Output Impedance
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Solution Overview
Problem
Existing level shift circuit arrangements face limitations in dynamic range and output impedance, with a trade-off between drive capability and power consumption, and often suffer from reduced current drive capability and high output impedance.
Innovation Solution
A push-pull amplifier with a totem pole configuration is introduced, featuring a MOSFET with a drain terminal connected to a current source and an amplifier stage that ensures constant channel current, providing class AB properties and low output impedance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a simple buffer structure with MOSFET is used for level shifting, then the circuit complexity is low, but the output impedance is high and dynamic range is reduced
Solution Approach 1:
The patent applies feedback by connecting the output of the buffer stage to the gate of the PMOS transistor in the totem pole configuration. This feedback mechanism allows the circuit to automatically adjust and maintain low output impedance across the full dynamic range by regulating the current flow through the level-shifting MOSFET based on the output voltage conditions.
Solution Approach 2:
The patent segments the buffer structure into multiple stages: a first buffer stage for initial level shifting and a second totem pole stage for impedance transformation. This segmentation allows each stage to perform its specific function optimally - the first stage handles the level shift while the second stage provides the low output impedance drive capability.
2Ease of operation
If feedback loop is added to reduce output impedance, then output impedance decreases, but power consumption increases due to bias current requirements
Solution Approach 1:
The patent employs dynamic current sharing between the PMOS and NMOS transistors in the totem pole configuration. The bias current is dynamically adjusted based on the operating conditions - when the output voltage requires level shifting, the current flows through the level-shifting MOSFET, and when no shifting is needed, the current is shared between the push-pull transistors, optimizing power consumption across different operating points.
Solution Approach 2:
The patent changes the effective resistance parameters of the circuit by using the gate-source voltage of the level-shifting MOSFET to control the current flow. By varying the Vgs parameter of the level-shifting transistor based on output conditions, the circuit dynamically adjusts its operating point to maintain low output impedance while minimizing unnecessary power dissipation.
3Power
If bias current is increased to improve current drive capability, then drive capability improves, but dynamic range is reduced due to voltage drops
Solution Approach 1:
The patent introduces the totem pole configuration with PMOS and NMOS transistors as an intermediary stage between the buffer and the load. This intermediary structure allows the bias current to be efficiently delivered to the load without creating excessive voltage drops at the buffer output, as the totem pole transistors act as controlled current sources that maintain proper voltage levels throughout the signal path.
Data Source
Figure 1A~2
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AI summary
A circuit arrangement comprises a circuit input (1), a circuit output (2), a first current source (11), a MOSFET (Mis) having a gate terminal, a source terminal and a drain terminal, and a push-pull amplifier (G); the gate terminal being connected with the circuit input (1), the drain terminal being coupled with the current source (11); the push-pull amplifier (G) having an input terminal (G_in) and an output terminal (G_out), the input terminal (G_in) being coupled to the first current source (11), the output terminal (G_out) being connected to the source terminal and the circuit output (2).