Level Shifter Bypass Switching for Lower Signal Delay

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Solution Overview

Problem

Level shifters in semiconductor devices experience delays and increased power consumption due to the number of transistors involved in signal traversal and static current buildup, especially when operating in voltage domains with low gate-source voltages.

Innovation Solution

A semiconductor device design that includes a level shifter and a switch module, where the switch controller determines whether the input voltage is higher or lower than the output voltage, allowing the switch module to bypass the level shifter when the input voltage is higher, thereby reducing signal delay and static current, and ensuring high gate-source voltages for efficient operation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a level shifter is used to shift signals between voltage domains, then voltage domain compatibility is improved, but signal delay increases due to the number of transistors involved

Engineering Contradiction:
Improvevoltage domain compatibilityVSAvoidsignal delay
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The patent implements dynamic voltage domain selection where the circuit can adaptively switch between different voltage domains based on operational requirements. The level shifter is selectively enabled or disabled, and different voltage domains (first voltage domain and second voltage domain) are dynamically selected to optimize performance, allowing the system to balance between voltage compatibility and signal delay characteristics.

Inventive Principle:
Principle #15Dynamics

2Use of energy by moving object

If a level shifter operates in voltage domains with low gate-source voltages, then lower voltage operation is achieved, but power consumption increases due to static current buildup

Engineering Contradiction:
Improvelower voltage operationVSAvoidpower consumption
Core Design Contradiction:
Use of energy by moving objectVSLoss of energy

Solution Approach 1:

The patent dynamically changes operating parameters including voltage domain selection and transistor gating states. By adjusting the gate-source voltage parameters and selectively enabling/disabling the level shifter based on operational mode, the circuit optimizes the balance between operating voltage level and power consumption, avoiding static current buildup while maintaining lower voltage operation capabilities.

Inventive Principle:
Principle #35Parameter changes

3Adaptability or versatility

If the level shifter is always enabled for voltage domain shifting, then voltage compatibility is maintained, but static current increases power consumption

Engineering Contradiction:
Improvevoltage domain shifting capabilityVSAvoidstatic current
Core Design Contradiction:
Adaptability or versatilityVSLoss of energy

Solution Approach 1:

The patent implements periodic or conditional activation of the level shifter rather than continuous operation. The circuit selectively enables the level shifter only when voltage domain shifting is actually required, and disables it during periods when direct connection suffices. This periodic action pattern maintains voltage domain compatibility when needed while eliminating static current consumption during normal operation.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS12143106B2Semiconductor device including a level shifter and method of mitigating a delay between input and output signals
Publication Date: 2024.11.12 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12143106B2 patent drawing
  • US12143106B2 patent drawing
  • US12143106B2 patent drawing

AI summary

A semiconductor device includes an input, a level shifter, an output, and a switch module. The input is configured to receive an input signal in a first voltage domain. The level shifter is connected to the input and is configured to shift the input signal from the first voltage domain to a second voltage domain. The switch module is configured to connect one of the input and the level shifter to the output. A method of mitigating a delay between input and output signals of the semiconductor device is also disclosed.