Integrated Level Shifter Latch for Metastability Across Voltage Domains
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Solution Overview
Problem
Integrated circuits operating in different clock and voltage domains face challenges in signal transmission due to frequency mismatches and voltage differences, leading to potential metastability issues and inefficient level shifting.
Innovation Solution
A circuit design that includes a level shifter and metastability resolution flop circuit, which generates true and complementary logic signals, stores them in a different voltage domain, and uses a latch circuit to provide a single-ended output, optimized for use with latches in a synchronizer to resolve metastability and adapt voltage levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If signals are transmitted between different voltage domains using conventional level shifters, then voltage level conversion is achieved, but metastability issues occur due to frequency mismatches between clock domains
Solution Approach 1:
The patent combines the level shifter circuit and metastability resolution circuit into a single integrated unit. The level shifter converts voltage levels between domains while the integrated metastability resolution circuit (using flip-flops or latches) simultaneously resolves timing issues, eliminating the need for separate circuits and improving overall signal reliability across voltage and clock domain boundaries
Solution Approach 2:
The patent introduces intermediate storage elements (flip-flops or latches) as mediators between different voltage and clock domains. These intermediaries temporarily hold signals during transition, allowing proper synchronization and metastability resolution while maintaining voltage level conversion, thus improving signal stability without sacrificing adaptability
2Reliability
If separate level shifter and metastability resolution circuits are used, then each function is performed independently, but circuit area and complexity increase
Solution Approach 1:
The patent merges the level shifter and metastability resolution circuits into a single integrated block. The level shifter circuitry is directly coupled with synchronization elements (flip-flops or latches), allowing both voltage conversion and metastability resolution to occur within one unified structure, thereby reducing overall circuit complexity while maintaining high signal transmission reliability
3Area of stationary object
If conventional level shifters are used without metastability resolution, then circuit area is reduced, but signal reliability deteriorates due to metastability
Solution Approach 1:
The patent integrates compact metastability resolution elements (such as single or double flip-flop structures or latch circuits) directly within the level shifter. This integration adds minimal area overhead while significantly improving data transfer reliability by ensuring proper synchronization and metastability handling occurs within the same voltage domain transition path
Data Source
AI summary
A level shifter and integrated level shifter and metastability resolution flop circuit are disclosed. A circuit includes a generation circuit, in a first voltage domain, coupled to receive a logic signal via a single-ended input and configured to generate true and complementary values of the logic signal. The circuit further includes a storage circuit coupled to receive the true and complementary values of the logic signal from the generation circuit. The storage circuit is configured to store the true and complementary values of the logic signal. The storage circuit is in a second voltage domain. The circuit further includes an output circuit coupled to the storage circuit and configured to provide a differential output signal having true and complementary values corresponding to the true and complementary values of the logic signal. The circuit may be combined with a latch circuit coupled to receive the differential output signal.