Level Shifter Circuit for Known Output States During Power-Up
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Solution Overview
Problem
In advanced system boards, level shifters face challenges during power-up when the core power voltage is not ready, leading to potential data contention, abnormal operations, and risk of permanent damage due to unknown voltage levels at the pad, as the input/output power voltage may be ready before the core power voltage.
Innovation Solution
The implementation of level shifters with first and second drivers that utilize AC coupling and switching elements to match the voltage level on the output terminals with the I/O power voltage when the core power voltage is not ready, ensuring predetermined logic states and preventing damage by setting output signals to known states during power-up.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the I/O power voltage is applied before the core power voltage is ready, then the I/O buffer can operate earlier, but the output pad may enter unknown states causing data contention and potential damage
Solution Approach 1:
The patent applies preliminary action by setting the output pad to a predetermined logic state (e.g., logic zero) before the core power voltage is ready. The first driver circuit is activated during the power-up phase to force the output pad into a known state, preventing undefined behavior. This preliminary configuration ensures that even though the I/O power voltage is applied early, the output remains controlled and predictable until the core logic unit is ready to provide valid signals.
2Device complexity
If the output pad is left floating during power-up, then the circuit design is simpler, but data contention and abnormal operations may occur
Solution Approach 1:
The patent introduces an intermediary first driver circuit that acts as a mediator between the power-up phase and the normal operation phase. This driver circuit is specifically designed to control the output pad during the transition period when core power voltage is not ready. It provides a buffer that prevents direct connection issues and ensures the pad maintains a valid logic state, thereby eliminating data contention without requiring major structural changes to the overall circuit design.
3Reliability
If the first driver circuit is always active, then the output pad is always protected, but power consumption increases
Solution Approach 1:
The patent applies dynamics by making the first driver circuit's operation conditional rather than continuous. The driver circuit is activated only during the power-up phase when the core power voltage is not ready and automatically deactivated when the core logic unit provides valid output signals. This dynamic control ensures the output pad is protected when needed while minimizing power consumption during normal operation, achieving a balance between reliability and energy efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively prevents data contention and abnormal operations by ensuring the output signals are set to predetermined states during power-up, even when the core power voltage is not ready, thereby preventing potential damage and ensuring stable operations.
Implementation Method 1
matching a voltage level on the first output terminal with the I/O power voltage by AC coupling when the core power voltage is not ready during power-up
Data Source
AI summary
Level shifters capable of setting logic level of the output signals thereof to a pre-defined known state during power-up are provided, in which a first logic unit is powered by a first power voltage, receives input signals with a core power voltage and comprises first and second output terminals. First and second drivers are coupled between the first output terminal and the first power voltage and between the second output terminal and the second power voltage respectively. When one of the first and second power voltages is not ready during power-up, the first driver matches a voltage level on the first output terminal with the first power voltage by AC coupling and the second driver pulls low or maintains a voltage level on the second output terminal.