Level Shifter Output Blocking for GPIO Power-Up Reset
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Solution Overview
Problem
Existing GPIO circuits face issues during system reset, where turning on the high voltage power supply first can inadvertently turn on the main driver, leading to incorrect states and potential leakage current, requiring additional complex control inputs and power-up detect circuits.
Innovation Solution
A level-up shifter with a cross-coupled pair of PFETs and protection logic that blocks output node switching during power-up, using internal voltage detection to ensure the main driver remains in a tri-state until both power supplies are powered up, eliminating the need for additional control inputs or power-up detect circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the high voltage power supply is turned on first during system reset, then the power-up sequence flexibility is improved, but the main driver may inadvertently turn on and enter an incorrect state causing leakage current
Solution Approach 1:
A protection logic circuit is introduced as an intermediary between the level-up shifter and the main driver. This protection logic monitors the voltage states at internal nodes and blocks the main driver from switching during the power-up phase, preventing incorrect states and leakage current while allowing flexible power-up sequences.
Solution Approach 2:
The protection logic detects voltage conditions at internal nodes before the main driver can switch, and proactively blocks the driver transition during power-up. This preliminary detection and blocking action prevents the harmful effect of incorrect driver states before they can occur, regardless of power-up sequence.
2Reliability
If additional control inputs and power-up detect circuits are added to prevent incorrect driver states, then the reliability is improved, but the device complexity and cost increase
Solution Approach 1:
The protection logic functionality is merged into the existing level-up shifter circuit structure, utilizing the same cross-coupled PFET configuration and internal nodes. This integration approach provides the necessary protection without adding separate dedicated control circuits, thereby reducing overall device complexity and cost.
Solution Approach 2:
The level-up shifter's internal nodes and existing circuit structure are used to detect power-up conditions and control the protection logic. The circuit serves itself by utilizing its own internal voltage states to trigger the blocking mechanism, eliminating the need for external power-up detect circuits and additional control inputs.
3Speed
If the level-up shifter allows output switching during power-up, then the operational speed is improved, but leakage current may occur due to incorrect driver states
Solution Approach 1:
The protection logic quickly detects the power-up condition through voltage monitoring of internal nodes and rapidly blocks the main driver switching during this critical phase. This fast detection and blocking action minimizes the time window for potential leakage current while allowing normal high-speed operation to resume once power-up is complete.
Data Source
AI summary
Embodiments of the disclosure provide an input output (IO) structure in which complimentary nodes of a level shifter are utilized to logically block the output of the IO structure from switching until both power supplies to the IO structure are powered up. An illustrative level shifter includes: a cross-coupled pair of PFETs configured to output complimentary voltage values at a first node and a second node; a control circuit configured to select which of the complementary voltage values are output to the first node and second node; a logic inverter having an input coupled to the first node and an output coupled to a third node; and a NAND gate having inputs coupled to the second node and third node and that generates a level shifted output.