Pulse-Triggered Level Shifter for Fast Low-Quiescent Transitions
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Solution Overview
Problem
Conventional level shifters face a trade-off between low quiescent currents and fast signal transitions, often consuming high static currents, which results in significant power loss, especially in gate driver circuits, while modern devices require lower quiescent currents and reduced propagation delays.
Innovation Solution
The proposed level shifter circuit incorporates a delay circuit, pulse generator, and latch circuit to generate short transitory latch signals, reducing quiescent power drain by activating current only during signal transitions, and utilizing logical AND circuits and switches to manage rising and falling edges, thereby minimizing static quiescent currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional level shifters are used to achieve fast signal transitions, then signal transition speed is improved, but quiescent current consumption increases significantly
Solution Approach 1:
The level shifter circuit employs periodic pulsed action instead of continuous operation. The delay circuit generates periodic delayed versions of the input signal, and the pulse generator creates narrow pulses only during signal transitions. This periodic pulsed operation allows the output to be updated only when necessary, minimizing continuous current draw while maintaining fast transition capability when signals change.
Solution Approach 2:
The circuit dynamically adjusts its operation based on signal transitions. The delay circuit and pulse generator are configured to activate current paths only during rising or falling edges of the input signal. During steady states, the circuit enters a low-power mode with minimal quiescent current. This dynamic behavior allows the circuit to provide fast transitions when needed while consuming minimal power during stable operation.
2Use of energy by moving object
If conventional level shifters are used to maintain low quiescent currents, then power consumption is reduced, but signal transition speed decreases
Solution Approach 1:
The delay circuit performs preliminary action by generating delayed versions of the input signal before the main switching action. These delayed signals are used by the pulse generator to create precisely timed narrow pulses that trigger the output transition. This preliminary preparation of timing signals ensures that when a transition is needed, it occurs rapidly and precisely, eliminating the need for continuous current flow to maintain readiness.
Solution Approach 2:
The delay circuit and pulse generator act as intermediary elements between the input signal and the output switching action. Instead of directly coupling the input to the output with continuous current paths, the intermediary delay-pulse mechanism translates input transitions into precise trigger pulses. This intermediary approach enables fast transitions on demand while maintaining low quiescent current during steady states.
3Speed
If continuous current paths are used in level shifters, then fast transitions are achieved, but static power loss increases
Solution Approach 1:
The circuit replaces continuous current paths with periodic pulsed current paths. The delay circuit generates periodic delayed signals that trigger narrow pulses only during transitions. This periodic action ensures current flows through the switching paths only when signal transitions occur, eliminating continuous static power loss while maintaining the capability for fast transitions when needed.
Solution Approach 2:
The circuit discards continuous current flow and recovers power by using narrow pulsed current only during transitions. The delay circuit and pulse generator are configured to eliminate current flow during steady states, effectively discarding the continuous power consumption. When transitions occur, the circuit recovers the necessary current flow temporarily to achieve fast switching, then returns to the low-power state.
Data Source
AI summary
One example discloses a level shifter circuit, including: an input port configured to receive an input signal (IN); an output port configured to transmit an output signal (OUT); a delay circuit coupled to generate a delayed input signal (IN_DLY) from the input signal (IN); a pulse generator coupled to the delay circuit and configured to generate a pulse signal from a combination of the input signal and the delayed input signal; and a latch circuit coupled to the pulse generator and configured to generate and hold a state of the output signal in response to the pulse signal.