Level Shifter Reduction in Nonvolatile Memory Decode Circuit
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Solution Overview
Problem
Nonvolatile memory systems require both positive and negative high voltage signals for word lines, making it challenging to reduce the number of level shifters while maintaining efficient signal decoding, as existing solutions are not adaptable to dual power supply systems.
Innovation Solution
A semiconductor device with a decode circuit that includes a level shifter to step up predecode signals and a logic gate to invert logical levels, allowing for different logical operations based on operation modes, reducing the number of level shifters needed by employing EXOR gates and high voltage logic circuits controlled by an inversion signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If level shifters are provided for each gate control signal and power supply line to convert low voltage to high voltage, then the nonvolatile memory can operate with proper voltage levels, but the occupied circuit area increases significantly
Solution Approach 1:
The patent applies universality by designing a single level shifter that can handle multiple gate control signals (Word L0, Word L1, Word R0, Word R1) and power supply lines through control signals. This multi-functional level shifter replaces what would traditionally require multiple separate level shifters, significantly reducing the occupied circuit area while maintaining the ability to convert low voltage to high voltage for all necessary signals
2Area of stationary object
If level conversion is performed before decoding with logical operation, then the number of level shifters can be reduced, but the decode circuit cannot handle both positive and negative high voltage signals required for nonvolatile memory
Solution Approach 1:
The patent applies dynamics by making the decode circuit adaptable to different operation modes (read, write, erase) through dynamic control signals. The circuit can switch between handling positive high voltage signals and negative high voltage signals based on the operation mode, enabling it to process both types of signals required for nonvolatile memory operations while maintaining a reduced number of level shifters
Solution Approach 2:
The patent uses control signals as intermediaries to coordinate between the level shifter and the decode circuit. These control signals enable the decode circuit to properly interpret and handle both positive and negative high voltage signals by providing contextual information about the current operation mode, allowing versatile signal handling without increasing the number of level shifters
Data Source
AI summary
The number of level shifters is reduced in a decode circuit of a nonvolatile memory. A semiconductor device is configured with an electrically rewritable nonvolatile memory cell array, and a decode circuit which generates a selection signal to select a driver for a memory gate line (word line). The decode circuit includes a level shifter to step up a signal after predecode. The selection signal is generated by decoding predecode signals which are stepped up by the level shifter in the logical operation circuit. A logic gate to invert the logical level of the predecode signal depending on an operation mode is provided in the preceding stage of each level shifter. When decoding the stepped-up predecode signal, the logical operation circuit performs a different logical operation depending on the operation mode.