Cross-Coupled Level Shifter Layout for Lower Delay and Shoot-Through
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Solution Overview
Problem
Conventional level shift circuits experience significant delays and shoot-through current due to increased complexity and die size, necessitating a solution that reduces power consumption and propagation delays while minimizing circuit complexity and die area.
Innovation Solution
A level shift circuit design featuring cross-coupled n-channel transistors with non-transitioning gates and relocated parasitic capacitances, which reduces shoot-through current and propagation delays without adding additional components or increasing die size, by maintaining gate-side nodes at a constant lower supply voltage and optimizing charge transfer through drain-to-source capacitors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If conventional level shift circuit design is used, then voltage level translation is achieved, but propagation delays increase and power consumption increases due to shoot-through current
Solution Approach 1:
The patent inverts the conventional level shifter architecture by placing n-channel transistors in the high voltage domain and p-channel transistors in the low voltage domain, opposite to the conventional arrangement. This inversion eliminates the need for complex shoot-through current suppression circuitry while reducing propagation delays and power consumption.
Solution Approach 2:
The patent changes the voltage domain parameters by operating n-channel transistors at high voltage and p-channel transistors at low voltage, rather than all transistors operating in the same voltage domain. This parameter change simplifies the circuit architecture and improves performance metrics.
2Loss of energy
If additional circuitry is added to reduce shoot-through current, then power consumption decreases, but device complexity and die size increase
Solution Approach 1:
The patent extracts and eliminates the shoot-through current problem by removing the need for additional suppression circuitry through the inverted transistor arrangement. The fundamental architecture change takes out the source of the problem rather than adding complex solutions.
Solution Approach 2:
The inverted transistor configuration is self-regulating, where the n-channel transistors in the high voltage domain and p-channel transistors in the low voltage domain automatically prevent shoot-through current without requiring additional control circuitry or components.
3Reliability
If conventional level shifter architecture is used, then voltage translation is achieved, but die area increases due to additional components
Solution Approach 1:
By inverting the conventional architecture and placing n-channel transistors in the high voltage domain with p-channel transistors in the low voltage domain, the patent achieves voltage translation with fewer components and reduced circuit complexity while maintaining reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly reduces propagation delays and minimizes circuit complexity and die size, improving level shifter performance by eliminating Miller multiplication effects and enhancing charge transfer efficiency.
Implementation Method 1
A first n-channel transistor pulls down an output signal from the higher supply voltage to a ground potential and with its non-transitioning gate held at the lower supply voltage
Implementation Method 2
A first p-channel transistor charges the output signal from the ground potential to the higher supply voltage
Implementation Method 3
relocating parasitic capacitances which reduces shoot-through current and propagation delays
Data Source
AI summary
Level shifting circuits and related methods are disclosed herein. The level shifting circuit includes a cross-coupled pull-up circuit coupled to a higher supply voltage, an output signal, and an inverted output signal. An input signal transitions between a ground and a lower supply voltage and an inverted input signal transitions in a direction opposite from the input signal between the ground and the lower supply voltage. A first n-channel transistor has a gate coupled to the lower supply voltage, a drain coupled to the output signal, and a source coupled to the inverted input signal. A second n-channel transistor has a gate coupled to the lower supply voltage, a drain coupled to the inverted output signal, and a source coupled to the input signal. The level shifting circuit may be included in an IC with core logic in a first voltage domain and input/output logic in a second voltage domain.