Cross-Coupled Level Shifter With Voltage Boosting for Fast I/O Translation
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Solution Overview
Problem
In modern integrated circuit (IC) design, the logical core and input/output unit often operate at different voltages, requiring a level shifter to ensure correct signal transmission, but existing level shifters lack rapid operation and compact size.
Innovation Solution
A level shifter design incorporating N-type and P-type transistors, along with voltage rising circuits, forms a differential input pair and cross-couples P-type transistors to operate within different voltage ranges, utilizing inverters and NAND gates to rapidly adjust voltage levels between the logical core and input/output unit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional level shifters are used to ensure correct signal transmission between different voltage ranges, then signal transmission reliability is improved, but operation speed becomes slow and device size increases
Solution Approach 1:
The patent employs dynamic voltage control through voltage rising circuits that actively adjust the voltage levels at the gates of P-type transistors based on the input signal state. This dynamic adjustment enables rapid switching between voltage ranges, significantly improving operation speed while maintaining reliable signal transmission between 1.2V and 3.3V domains
Solution Approach 2:
The voltage rising circuits perform preliminary voltage preparation by pre-charging the gates of P-type transistors to the second power level before the actual switching operation. This preliminary action reduces the switching time and enables faster operation while ensuring correct logical state transitions
2Reliability
If conventional level shifters are used to ensure correct signal transmission between different voltage ranges, then signal transmission reliability is improved, but device size increases
Solution Approach 1:
The patent merges the voltage level shifting function with differential signal processing in a single integrated circuit structure. The differential input pair and cross-coupled P-type transistors with voltage rising circuits are combined to perform both differential amplification and voltage level conversion simultaneously, reducing the overall device area compared to separate stages
Solution Approach 2:
The patent utilizes parameter changes in transistor sizing and voltage levels to optimize the circuit. By carefully selecting transistor widths and lengths, and by using different power levels (1.2V and 3.3V), the circuit achieves reliable signal transmission with compact transistor dimensions, reducing the overall device footprint
3Area of stationary object
If transistor size is reduced to achieve compact design, then device size is reduced, but operation speed may decrease
Solution Approach 1:
The voltage rising circuits dynamically adjust the gate voltages of P-type transistors to the higher second power level during switching operations. This dynamic voltage boosting compensates for the reduced transistor size effects, maintaining strong drive capability and fast switching speed even with smaller transistor dimensions
Solution Approach 2:
The patent employs a composite circuit architecture combining N-type differential input transistors with P-type cross-coupled transistors and voltage rising circuits. This composite structure leverages the complementary strengths of different transistor types and voltage levels to achieve both compact size and high-speed operation
Data Source
AI summary
A level shifter having first and second P-type transistors cross coupled at an output port thereof, wherein there are first and second voltage rising circuits coupled at gates of the first and second P-type transistors, respectively. A voltage level at the gate of the first P-type transistor is associated with an output signal of the level shifter. When an input signal, operated by a first power, of the level shifter rises, the first voltage rising circuit couples a second power to the gate of the first P-type transistor to speed up the rising of the output signal. The voltage level at the gate of the second P-type transistor is associated with an inverted output signal. When the input signal falls, the second voltage rising circuit couples the second power to the gate of the second P-type transistor to speed up the rising of the inverted output signal.