Level Shifter Protection Circuit for Wide Voltage Margins
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Solution Overview
Problem
Conventional level shifters struggle to achieve a wide margin level shift due to the limited withstand voltage of transistors, which cannot handle higher voltage upper limits in different power domains.
Innovation Solution
The proposed level shifter incorporates a latch circuit, a clamping circuit, a protection circuit, and an input circuit, which collectively enable a wide margin level shift by managing voltage drops and limiting output voltage ranges, thereby overcoming transistor voltage limitations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If transistors with higher withstand voltages are used in the latch circuit, then the level shift margin can be increased, but the transistor manufacturing becomes more difficult and costly
Solution Approach 1:
The level shifter is divided into multiple functional blocks: input circuit (310), protection circuit (320), clamping circuit (330), and latch circuit (340). Each block operates at different voltage levels and provides specific functions. The protection circuit uses first and second protection transistor pairs to create voltage drops, while the clamping circuit uses third and fourth protection transistor pairs to limit output voltage. This segmentation allows the use of standard transistors in each block rather than requiring all transistors to withstand the maximum voltage.
Solution Approach 2:
The protection circuit and clamping circuit act as intermediary blocks between the input circuit and the latch circuit. These intermediary circuits create and limit voltage drops, respectively, to protect the latch circuit transistors from exceeding their withstand voltage. The first protection transistor pair creates a first voltage drop, the second protection transistor pair creates a second voltage drop, the third protection transistor pair limits the upper limit of output voltage, and the fourth protection transistor pair limits the lower limit of output voltage.
2Adaptability or versatility
If the output voltage range is extended to higher voltages, then the level shift capability is improved, but the transistor reliability decreases due to exceeding withstand voltage
Solution Approach 1:
The protection circuit performs preliminary action by creating voltage drops before the signal reaches the latch circuit. The first protection transistor pair creates a first voltage drop and the second protection transistor pair creates a second voltage drop, reducing the voltage level before it enters the latch circuit. This preliminary voltage reduction ensures that the latch circuit transistors are not exposed to voltages exceeding their withstand capability.
Solution Approach 2:
The clamping circuit provides feedback control to limit the output voltage range. The third protection transistor pair limits the upper limit of the output voltage, and the fourth protection transistor pair limits the lower limit of the output voltage. This feedback mechanism ensures that the output voltage stays within safe boundaries that protect the transistor reliability while still achieving the desired level shift capability.
Data Source
AI summary
A level shifter can achieve a level shift by a wide margin. The level shifter includes a latch circuit, a protection circuit, and an input circuit. The latch circuit is coupled between a high-voltage terminal and the protection circuit. The protection circuit including a first protection transistor pair and a second protection transistor pair is set between the latch circuit and the input circuit, and is configured to prevent an excessive voltage drop between the input circuit and a pair of output terminals, wherein the pair of output terminals is set between the first and the second protection transistor pairs and used for outputting a pair of output signals. The input circuit includes an input transistor pair coupled between the second protection transistor pair and a low-voltage terminal and configured to operate according to a pair of input signals.