Level Shifter Transistor Layout for Fast Voltage-Domain Switching

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Solution Overview

Problem

Existing electronic circuits with level shifters struggle to transmit signals quickly and reliably between different voltage domains.

Innovation Solution

The electronic circuit incorporates a level shifter transistor with a load path coupled between a low-side reference node and a high-side supply node, integrated in a semiconductor body with a base region, tub, and device region of specific doping types, allowing for efficient signal transmission.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If a conventional level shifter is used to transmit signals between different voltage domains, then signal transmission between voltage domains is achieved, but the signal transmission speed is slow and reliability is poor

Engineering Contradiction:
Improvesignal transmission speedVSAvoidsignal transmission reliability
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The level shifter is divided into two independent transistors (first level shifter transistor and second level shifter transistor) with separate load paths. Each transistor handles one polarity of the signal independently, allowing simultaneous operation and faster signal transmission while maintaining reliability through redundancy and isolation of failure modes.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Both level shifter transistors are integrated into a single semiconductor body with shared structural components (base region, tub, device region). This merging provides electrical isolation through the tub structure while enabling compact integration and simultaneous operation, achieving both speed and reliability.

Inventive Principle:
Principle #5Merging (Combining)

2Speed

If a level shifter transistor is integrated in a semiconductor body with base region, tub, and device region, then switching speed is improved, but device complexity increases

Engineering Contradiction:
Improveswitching speedVSAvoidsemiconductor structure complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The tub structure serves multiple functions: it provides electrical isolation between the first and second level shifter transistors, defines the device region boundaries, and enables the complementary doping type configuration. This multi-functionality reduces the need for additional isolation structures and simplifies the overall device architecture while maintaining high switching speed.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The semiconductor body uses different doping types in specific regions (base region of first doping type, tub of second doping type, device region of first doping type). This localized doping strategy creates optimal electrical characteristics for fast switching in each region while maintaining a relatively simple overall structure that can be manufactured using standard semiconductor processes.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20250192781A1Electronic circuit including a level shifter
Publication Date: 2025.06.12 INFINEON TECH DRESDEN GMBH & CO KG
  • US20250192781A1 patent drawing
  • US20250192781A1 patent drawing
  • US20250192781A1 patent drawing

AI summary

An electronic circuit and an integrated circuit are disclosed. The electronic circuit includes: a level shifter including a level shifter transistor having a load path coupled between a low-side reference node and a high-side supply node of the electronic circuit. The electronic circuit further includes a semiconductor body having a base region of a first doping type, a tub of a second doping type complementary to the first doping type, and a device region of the first doping separated from the base region by the tub. The level shifter transistor is at least partially integrated in the device region, and the tub is connected to the high-side supply node and the base region is connected to the low-side reference node.