Linear Decimation Filters for Delta-Sigma Noise Suppression
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Incremental delta-sigma analog-to-digital converters face challenges in energy reduction from modulators, and existing decimation filters do not effectively suppress quantization noise while maintaining a low thermal noise penalty.
Innovation Solution
The derivation and analysis of two linear decimation filters, L2min2 and its symmetric version L2min2s, which offer strong quantization noise suppression and low thermal noise penalty, outperforming traditional filters like CoI1, CoI2, CoI3, sinc2, or sinc3 filters, and are suitable for first- and second-order IDC output decimation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional decimation filters (CoI1, CoI2, CoI3, sinc2, sinc3) are used, then the implementation is straightforward, but quantization noise suppression is insufficient and thermal noise penalty is high
Solution Approach 1:
The patent changes the filter parameters by deriving new linear decimation filters (L2min2 and L2min2s) with optimized coefficients specifically tailored for incremental delta-sigma converters. These filters use different weighting parameters and structure compared to traditional filters, achieving superior quantization noise suppression while maintaining low thermal noise penalty through mathematical optimization of the decimation process
Solution Approach 2:
The patent replaces the conventional mechanical filter design approach with a mathematically optimized linear filtering system. By substituting traditional filter architectures with newly derived linear filters that have optimized transfer functions, the system achieves better noise performance without the thermal noise penalties associated with conventional approaches
2Use of energy by moving object
If modulator design is optimized to reduce energy consumption, then energy efficiency improves, but further energy reduction becomes increasingly difficult
Solution Approach 1:
The patent extracts the energy optimization problem from the modulator and relocates it to the decimation filter stage. By taking out the energy efficiency challenge from the modulator design and addressing it through filter optimization instead, the system achieves overall energy efficiency improvements without being constrained by modulator design limitations
Solution Approach 2:
The decimation filter serves as an intermediary component that bridges the modulator and output stages. By optimizing this intermediary filter, the system achieves energy efficiency improvements indirectly, allowing the modulator to operate at its natural efficiency while the filter provides the additional optimization layer
3Measurement precision
If higher-order modulators are used to improve resolution, then conversion accuracy increases, but the complexity of deriving efficient filters increases
Solution Approach 1:
The patent segments the filter design process by providing systematic derivation methods for different modulator orders. By breaking down the complex derivation into structured approaches for first-order and second-order modulators specifically, the system achieves high resolution conversion while managing complexity through methodical design procedures
Solution Approach 2:
The derived linear filters are designed to be universal solutions that work effectively for both first-order and second-order incremental delta-sigma converters. This multi-functionality allows the same filtering approach to serve multiple modulator orders, reducing the overall complexity of filter derivation and implementation across different resolution requirements
Data Source
AI summary
Linear decimation filters for incremental delta-sigma analog to digital converters are provided with a data rate signal input; a digital signal input; a weight generator connected to the signal input to generate a weight signal via a weight signal output; an adder having a digital signal output, a first addition input connected to the weight signal output, and a second addition input connected to the digital signal output; and an AND-gate having a first input connected to the input data rate signal input and a second input connected to the digital signal input to produce a logical output that gates output from the digital signal output of the adder.