Links and Chains Verification for System-on-Chip Validation
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Solution Overview
Problem
The complexity of systems on a chip (SoC) makes it challenging for silicon designers to verify and validate devices without knowledge of the end application, leading to costly delays and inefficiencies in identifying bugs and releasing functional devices.
Innovation Solution
The Links and Chains (LNC) methodology provides a hierarchical and systematic approach to verification and validation, blending bottom-up and top-down methods to create objective metrics and reuse test cases, ensuring a fully tested device before tape-out, using chip support libraries and diagnostics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional verification and validation is performed on each megacell separately, then verification coverage is improved, but verification time and complexity increase significantly
Solution Approach 1:
The patent combines multiple megacell verification processes into a single integrated verification framework. The testbench integrates CPU, DSP, image processor, video port, memory interface, and peripheral interface into one unified verification system that can execute tests across all megacells simultaneously, reducing total verification time while maintaining comprehensive coverage.
Solution Approach 2:
The verification process is segmented into hierarchical levels: megacell-level verification, chip-level verification, and system-level verification. Each level has specific test matrices and test cases that can be executed independently or in combination, allowing flexible verification scheduling and resource allocation.
2Measurement precision
If detailed test matrices and test cases are developed for each megacell, then verification precision is improved, but device complexity and resource requirements increase
Solution Approach 1:
The testbench is designed as a universal verification platform that can verify multiple megacells using a common set of verification primitives, test matrices, and diagnostic tools. This multi-functional approach reduces the need for separate verification infrastructure for each megacell while maintaining precise verification capabilities.
Solution Approach 2:
The patent uses modular test case templates that can be copied and adapted for different megacells. Test matrices are structured as reusable templates that can be instantiated for various megacell configurations, reducing the manual effort required to create verification tests while maintaining precision.
3Reliability
If verification is completed before tape-out commitment, then device reliability is improved, but time-to-market is reduced
Solution Approach 1:
The verification process is performed as a preliminary action before tape-out commitment. The testbench is configured to execute comprehensive verification tests on all megacells and interfaces before the design is committed to manufacturing. This ensures that all bugs are identified and fixed before tape-out, improving device reliability without requiring post-manufacturing corrections.
Solution Approach 2:
The verification process operates continuously throughout the design cycle rather than as a final step. Verification tests are executed iteratively as design changes occur, ensuring continuous validation of functionality. This continuous verification approach maintains reliability while enabling faster iteration and reduced time-to-market.
Data Source
AI summary
The links and chains (LNC) of this invention is an applications verification and validation (AVV) methodology. LNC is a hierarchical and systematic approach emphasizing conservation and reuse of effort expended. LNC creates objective metrics for validation. This invention ensures that the device will work in a system environment. LNC is an independent and complementary validation of the design before committing release to tape-out. The chip support library (CSL) and diagnostics used by LNC are natural outputs of the validation and are thus gating items to tape-out release. This ensures a fully tested device.