Lithography Optimization for Semiconductor Feature Fidelity
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The semiconductor industry faces challenges in achieving high fidelity between as-drawn and imaged features during IC manufacturing, particularly due to limitations in lithography tools, leading to poorly shaped device features and increased complexity in processing and manufacturing as technology scales down.
Innovation Solution
A system and method that identifies critical portions of IC features, assigns specific image criteria, and determines optimized lithography parameters to enhance fidelity, allowing for asymmetric imaging of symmetric features by applying different lithography optimization parameters to different portions of a feature, thereby improving manufacturing efficiency and accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If rule or model based corrections (OPC) are performed on entire design to reach desired fidelity, then imaging fidelity improves, but time and resource consumption increases
Solution Approach 1:
The patent applies different image criteria to different portions of the same feature based on their criticality. Critical portions (e.g., edges adjacent to other features) receive higher image criteria and more aggressive OPC corrections, while non-critical portions use lower image criteria and minimal corrections. This selective approach maintains necessary fidelity only where required, reducing overall processing time and resources.
Solution Approach 2:
The patent segments features into multiple portions with different criticality levels. Each portion is independently evaluated and assigned appropriate image criteria. This segmentation allows the OPC process to focus computational resources on critical areas rather than uniformly processing entire features, thereby reducing total processing time while maintaining necessary fidelity.
2Manufacturing precision
If symmetric features are imaged using standard lithography, then manufacturing simplicity is maintained, but imaging fidelity deteriorates due to lithography tool limitations
Solution Approach 1:
The patent intentionally introduces asymmetry into the lithography process by applying different image criteria to different portions of symmetric features. Critical portions receive enhanced corrections while non-critical portions use standard processing. This selective asymmetry compensates for lithography tool limitations and achieves higher overall fidelity without requiring complete redesign of the manufacturing process.
Solution Approach 2:
The patent changes lithography parameters (image criteria values) based on the criticality of different feature portions. By dynamically adjusting parameters such as focus, exposure, and correction strength according to local requirements, the system achieves high fidelity imaging without requiring fundamentally new lithography tools or processes.
3Productivity
If resources are concentrated on critical areas only, then manufacturing efficiency improves, but overall feature quality may deteriorate
Solution Approach 1:
The patent ensures that every portion of a feature receives appropriate quality treatment based on its criticality. Critical portions receive high-quality corrections with stringent image criteria, while non-critical portions receive streamlined processing with relaxed criteria. This localized quality approach maintains necessary overall feature quality while optimizing manufacturing efficiency by avoiding excessive processing on non-critical areas.
Data Source
AI summary
In a method, a layout of a device having a pattern of features is provided. The method continues to include identifying a first portion of at least one feature of the plurality of features. An image criteria for the first portion may be assigned. A lithography optimization parameter is determined based on the assigned image criteria for the first portion. Finally, the first portion of the at least one feature is imaged onto a semiconductor substrate using the determined lithography optimization parameter.