LNA Mid-Node Impedance Network for Gain and Input Matching

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Solution Overview

Problem

Low noise amplifiers (LNAs) face a trade-off between gain and reflection coefficient, where improving gain often degrades reflection coefficient and vice versa, limiting their flexibility in achieving optimal S11 and noise figure specifications due to parasitic capacitance effects.

Innovation Solution

Incorporating a mid-node impedance network between the transconductance and cascode devices, which can include resistors, capacitors, and inductors, to compensate for parasitic capacitance and decouple the design trade-off between reflection coefficient and gain, allowing for greater flexibility in achieving desired performance metrics.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If gain is improved in LNA design, then amplification capability increases, but reflection coefficient degrades

Engineering Contradiction:
ImprovegainVSAvoidreflection coefficient
Core Design Contradiction:
PowerVSObject-affected harmful factors

Solution Approach 1:

A mid-node impedance network is introduced between the common-source transistor and common-gate transistor to act as an intermediary element. This network includes impedance compensation elements (capacitors C1-C4 and inductors L1-L4) that mediate the interaction between the two transistors, allowing gain improvement while maintaining reflection coefficient specifications by compensating for parasitic capacitance effects.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The impedance network changes the electrical parameters at the mid-node by introducing compensating capacitive and inductive elements. These parameter changes counteract the parasitic capacitance of the common-source transistor, enabling the design to achieve both high gain and good input matching simultaneously by adjusting the effective impedance seen by the signal.

Inventive Principle:
Principle #35Parameter changes

2Device complexity

If parasitic capacitance effects are not compensated, then device complexity remains low, but performance degradation occurs

Engineering Contradiction:
Improvecircuit structureVSAvoidperformance specification
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The mid-node impedance network serves as an intermediary structure that systematically addresses parasitic capacitance effects. By inserting this dedicated compensation network between the common-source and common-gate stages, the design achieves reliable performance specifications for both gain and reflection coefficient without excessive overall complexity, as the network is localized and targeted.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS10615756B2Apparatus and methods for low noise amplifiers with mid-node impedance networks
Publication Date: 2020.04.07 SKYWORKS SOLUTIONS INC
  • US10615756B2 patent drawing
  • US10615756B2 patent drawing
  • US10615756B2 patent drawing

AI summary

Apparatus and methods for LNAs with mid-node impedance networks are provided herein. In certain configurations, an LNA includes a mid-node impedance circuit including a resistor and a capacitor electrically connected in parallel, a cascode device electrically connected between an output terminal and the mid-node impedance circuit, and a transconductance device electrically connected between the mid-node impedance circuit and ground. The transconductance device amplifies a radio frequency signal received from an input terminal. The LNA further includes a feedback bias circuit electrically connected between the output terminal and the input terminal and operable to control an input bias voltage of the transconductance device.