Load-Adaptive Noise Tolerance Testing for Logic Cells
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing circuit design verification methods suffer from false noise violations due to inadequate noise tolerance testing, leading to resource wastage and reduced productivity.
Innovation Solution
A computer-implemented method that provides multiple noise tolerance data curves for different capacitive loads on logic cells, allowing for adaptive noise impact testing by selecting a tailored noise tolerance curve based on the actual capacitive load, thereby reducing false noise violations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional noise tolerance testing with fixed thresholds is used, then testing simplicity is maintained, but false noise violations occur leading to reduced productivity
Solution Approach 1:
The patent implements dynamic noise tolerance thresholds by generating multiple noise tolerance data curves corresponding to different capacitive load conditions. Instead of using a fixed threshold, the system adaptively selects or interpolates between curves based on the actual capacitive load of the logic cell instance being tested. This dynamic approach reduces false noise violations while maintaining testing reliability, directly addressing the contradiction between productivity and accuracy.
Solution Approach 2:
The patent changes the noise tolerance parameter from a fixed value to a variable that depends on capacitive load conditions. By obtaining multiple noise tolerance data curves for different capacitive loads and selecting the appropriate curve based on the actual load, the system adjusts the noise tolerance parameter to match real operating conditions. This parameter adaptation eliminates false violations and improves both productivity and testing accuracy.
2Reliability
If multiple noise tolerance data curves for different capacitive loads are implemented, then false noise violations are reduced, but device complexity increases
Solution Approach 1:
The patent performs preliminary action by pre-obtaining multiple noise tolerance data curves for different capacitive load conditions before actual noise testing. These curves are stored and readily available when needed. By preparing the tolerance data in advance rather than calculating it dynamically during testing, the system reduces computational complexity while maintaining high reliability in noise violation detection.
Solution Approach 2:
The patent introduces an intermediary mechanism (the set of pre-computed noise tolerance data curves) that mediates between the simple fixed-threshold approach and the complex real-time calculation approach. These intermediate curves serve as lookup tables that provide accurate noise tolerance values without requiring complex real-time computations, thus reducing system complexity while improving reliability.
3Productivity
If adaptive noise tolerance testing is performed by selecting curves based on capacitive load, then resource utilization is optimized, but measurement precision requirements increase
Solution Approach 1:
The patent applies partial action by using a discrete set of noise tolerance data curves for specific capacitive load values rather than requiring continuous precision measurements. The system selects the closest matching curve from the pre-computed set based on the measured capacitive load, which relaxes the precision requirements while still providing adaptive testing that optimizes resource utilization and reduces false violations.
Data Source
AI summary
A load adaptive process is provided for noise impact on function testing of circuit design logic cells. The process includes obtaining multiple noise tolerance data curves for different potential capacitive loads on a logic cell. The process includes performing noise impact on function testing of an instance of the logic cell within the circuit design. The performing includes selecting, based on a capacitive load of the logic cell instance of the circuit design, a noise tolerance data curve of the multiple curves, and determining whether the logic cell instance fails noise impact on function testing based on comparing a noise pulse at the logic cell instance to the selected noise tolerance data curve. Further, the process includes initiating, based on the logic cell instance of the circuit design failing the noise impact on function testing, one or more actions to facilitate addressing the failing of the logic cell instance.