Load Lock Chamber Sequencing to Minimize Wafer Processing Vibration

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Charged particle beam devices face challenges in achieving high throughput due to vibrations from mechanisms like pipe opening/closing valves and shutter operations, which result in waiting times and reduced precision during semiconductor wafer processing.

Innovation Solution

A semiconductor processing apparatus with a control mechanism that coordinates the operations of load lock chambers to minimize vibrations by performing vibration-generating operations in chambers not exchanging wafers with the sample chamber, thereby reducing waiting times and improving throughput.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If pipe opening/closing valve operations are performed during wafer processing, then vacuum control is achieved, but vibrations occur causing waiting time and reduced throughput

Engineering Contradiction:
Improvevacuum controlVSAvoidthroughput
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The system divides the single load lock chamber into multiple load lock chambers (first and second load lock chambers), allowing vacuum control operations in one chamber while wafer processing occurs in another, thereby segmenting the functions to eliminate vibrations during processing

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The sample exchange mechanism acts as an intermediary between the load lock chambers and the processing chamber, enabling coordinated operation where wafer transfer occurs during vibration-free periods while vacuum operations occur in parallel in separate chambers

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of operation

If shutter operations are performed during wafer processing, then sample carry-in port control is achieved, but vibrations occur causing waiting time and reduced throughput

Engineering Contradiction:
Improvesample carry-in port controlVSAvoidthroughput
Core Design Contradiction:
Ease of operationVSProductivity

Solution Approach 1:

The system separates shutter operations into different chambers at different times - the first shutter operates in the first load lock chamber while the second shutter remains closed during wafer processing, eliminating vibration interference with the processing operation

Inventive Principle:
Principle #1Segmentation

3Productivity

If multiple load lock chambers are used to parallelize operations, then throughput is improved, but device complexity increases

Engineering Contradiction:
ImprovethroughputVSAvoidnumber of load lock chambers
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

Each load lock chamber is designed with identical multi-functional capabilities, serving as both a vacuum isolation chamber and a processing preparation chamber, allowing the system to handle multiple wafers through parallel operations while maintaining standardized chamber designs

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20240404780A1Semiconductor processing apparatus
Publication Date: 2024.12.05 HITACHI HIGH TECH CORP
  • US20240404780A1 patent drawing
  • US20240404780A1 patent drawing
  • US20240404780A1 patent drawing

AI summary

A plurality of load lock chambers are provided, a predetermined valve device is controlled such that the valve device is not operated during wafer processing, a signal for permitting operation of the predetermined valve device is transmitted at a timing when the wafer processing is completed, and the valve device is operated based on the signal. Thus, while a processed wafer and an unprocessed wafer are exchanged between one load lock chamber and a processing chamber, an operation sequence of the entire semiconductor processing apparatus is controlled such that a predetermined valve device in the other load lock chamber is operated, and thus vibration does not occur during the operation of an electron optical system, thereby reducing a waiting time.