Load Store Circuitry Shared Memory Access for Atomic Data Transfers
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Solution Overview
Problem
Processor designs face challenges in efficiently handling single-copy-atomic load/store instructions for large data blocks, as the existing load/store data path may not support the maximum data size required, leading to increased hardware costs and complexity.
Innovation Solution
The solution involves mapping a single-copy-atomic load/store instruction to a plurality of mapped load/store micro-operations, which trigger a shared memory access request and separate transfers over a narrower data path, maintaining atomicity while reducing hardware costs by avoiding the need for a wider data path.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the load/store data path is widened to support large data blocks, then the maximum data size supported increases, but hardware costs and complexity increase
Solution Approach 1:
The patent divides a large data block transfer operation into multiple smaller micro-operations, each handling a portion of the data that fits within the existing data path width. The instruction decoder breaks down a single large load/store instruction into multiple micro-operations that can be processed sequentially through the existing narrow data path, eliminating the need to widen it.
Solution Approach 2:
The patent introduces a buffer as an intermediary component between the narrow load/store data path and the large data block in memory. The buffer temporarily stores data portions as they are transferred, allowing the narrow data path to handle small chunks while ultimately supporting large data block transfers without requiring data path widening.
2Device complexity
If multiple micro-operations are used to handle large data blocks, then hardware costs are reduced, but the number of processing steps increases
Solution Approach 1:
The patent ensures continuous data transfer by pipeline-izing the micro-operations. While one micro-operation is transferring data, the next is being prepared, and previous operations are completing. This continuous flow minimizes idle time and reduces the overall processing time despite using multiple micro-operations.
Solution Approach 2:
The instruction decoder performs preliminary breakdown of the large load/store instruction into multiple micro-operations before execution. This preparation allows the execution units to process them efficiently in sequence without needing to perform complex analysis during execution, reducing processing overhead.
3Productivity
If a shared memory access request is used for multiple micro-operations, then resource utilization improves, but coordination complexity increases
Solution Approach 1:
The patent merges multiple micro-operations into a single shared memory access request when they target the same memory address. This consolidation reduces the total number of memory access requests, improving resource utilization by allowing the memory system to handle fewer, larger transfers rather than multiple small ones.
Solution Approach 2:
The load/store buffer tracks the state of each micro-operation and provides feedback to the memory access request generation logic. This feedback mechanism allows the system to intelligently determine when multiple micro-operations can share a memory request, automatically managing the coordination complexity through state monitoring and conditional merging.
Data Source
AI summary
In response to a single-copy-atomic load/store instruction for requesting an atomic transfer of a target block of data between the memory system and the registers, where the target block has a given size greater than a maximum data size supported for a single load/store micro-operation by a load/store data path, instruction decoding circuitry maps the single-copy-atomic load/store instruction to two or more mapped load/store micro-operations each for requesting transfer of a respective portion of the target block of data. In response to the mapped load/store micro-operations, load/store circuitry triggers issuing of a shared memory access request to the memory system to request the atomic transfer of the target block of data of said given size to or from the memory system, and triggers separate transfers of respective portions of the target block of data over the load/store data path.