Loadable TSPC Flip-Flop for High-Speed State Loading
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Solution Overview
Problem
True-single-phase-clocking (TSPC) flops typically operate at high speeds with low power and area consumption but have limitations due to high-impedance nodes, which restrict their minimum frequency operation and lack the ability to load and maintain specific states, making them unsuitable for applications requiring state loading.
Innovation Solution
A loadable TSPC flop circuit is designed to operate in normal, reset loading, and set loading modes by using a set/reset toggle block and precharge network, allowing the output node to be loaded and held to specific values through control signals, thereby enabling state loading without impacting maximum clock speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If TSPC flop uses high-impedance nodes to operate at high speeds with low power consumption, then speed and power efficiency are improved, but the minimum frequency operation is restricted and state loading capability is lost
Solution Approach 1:
The patent applies dynamics by making the TSPC flop's impedance characteristics changeable through control signals. The flop can dynamically switch between high-impedance mode (for high-speed operation) and low-impedance mode (for state loading and holding), allowing it to adapt to different operational requirements without sacrificing either speed or loading capability
Solution Approach 2:
The patent changes the electrical parameters (impedance levels) of the TSPC flop nodes based on operational mode. By adjusting impedance parameters dynamically, the flop maintains high-speed performance during normal operation while enabling state loading functionality when needed, resolving the contradiction between speed and adaptability
2Productivity
If TSPC flop operates in always-running configuration to maintain high speed, then productivity is improved, but the ability to load and maintain specific states is lost
Solution Approach 1:
The flop dynamically adjusts its operational characteristics based on control signals. During normal high-speed operation, it maintains always-running behavior for maximum productivity. When state loading is required, it transitions to a mode that accepts and holds specific states, making it easy to control and load without sacrificing overall productivity
3Adaptability or versatility
If loading functionality is added to TSPC flop, then adaptability is improved, but device complexity increases
Solution Approach 1:
The patent implements multi-functionality by designing the TSPC flop to perform both high-speed counting operations and state loading functions using a unified circuit structure. The same flip-flop circuit handles both normal toggling operation and loaded state maintenance, reducing overall device complexity compared to using separate circuits for each function
Solution Approach 2:
The patent merges the state loading functionality into the existing TSPC flop circuit rather than adding separate loading circuitry. By combining the loading control logic with the differential flip-flop structure, the patent reduces device complexity while maintaining adaptability
Data Source
AI summary
Techniques are described for implementing a true-single-phase-clocking (TSPC) flop with loading functionality. For example, the a loadable TSPC flop can receive input signals, including at least a clock input signal, a SET signal, and a RESET signal. Responsive to one configuration of the input signals, the loadable TSPC flop operates in a normal mode, in which its output node toggles responsive to the clock input signal. Responsive to another configuration of the input signals, the loadable TSPC flop operates in a reset loading mode, such that the Qb output node is loaded and held to a predetermined reset value. Responsive to another configuration of the input signals, the loadable TSPC flop operates in a set loading mode, such that the Qb output node is loaded and held to a predetermined set value that is a complement of the predetermined reset value.