Local Interconnect for Semiconductor Area Reduction
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Solution Overview
Problem
Conventional semiconductor devices experience malfunctions and variations in transistor characteristics due to rounding of impurity diffusion regions, which increases chip area and reduces integration and speed.
Innovation Solution
A semiconductor device design featuring local interconnects formed in contact with the upper surface of impurity diffusion regions, extending to below the potential supply interconnect, eliminating the need for metal interconnects and reducing area without causing variations in transistor characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the source region of each transistor extends to the boundary between standard cells to be coupled to a power supply interconnect, then the interconnect resource is secured and the area of the standard cell is reduced, but rounding of the impurity diffusion region causes malfunctions and variations in transistor characteristics
Solution Approach 1:
The patent introduces a local interconnect as an intermediary element between the impurity diffusion region and the power supply interconnect. This local interconnect is formed in contact with the upper surface of the impurity diffusion region and extends to below the power supply interconnect, serving as a mediator that eliminates the need for the impurity diffusion region to extend to the boundary, thereby preventing rounding-induced malfunctions while maintaining area efficiency.
2Reliability
If metal interconnects are used to connect the source region to the power supply interconnect, then reliable electrical connection is achieved, but the chip area increases
Solution Approach 1:
The patent employs the local interconnect structure that utilizes the impurity diffusion region's own upper surface for contact, eliminating the need for separate metal interconnect layers. The local interconnect extends vertically to below the power supply interconnect, allowing electrical connection without consuming additional horizontal chip area, thus achieving area-efficient reliable connection.
3Length of moving object
If the impurity diffusion region is extended to reduce area, then standard cell height is reduced, but transistor characteristics become unstable due to rounding effects
Solution Approach 1:
The patent transitions the connection approach from horizontal extension of the impurity diffusion region to vertical extension via the local interconnect. The local interconnect extends in the vertical dimension below the power supply interconnect, allowing the standard cell height to be optimized without requiring the impurity diffusion region to extend horizontally to the boundary, thereby avoiding rounding effects and maintaining manufacturing precision.
Data Source
AI summary
A local interconnect is formed in contact with an upper surface of an impurity diffusion region and extends to below a potential supply interconnect. A contact hole electrically couples the local interconnect to the potential supply interconnect. The local interconnect, which is formed in contact with the upper surface of the impurity diffusion region, is used for electrically coupling the impurity diffusion region to the potential supply interconnect.