Local Interconnection Layer for Semiconductor Device Density
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Solution Overview
Problem
The miniaturization of semiconductor devices is limited by process and design rules, particularly due to constraints on spacer size, contact hole dimensions, and distance from groove isolation regions, which restrict further reduction in device density and increase costs with advanced reticle technologies.
Innovation Solution
A method of manufacturing semiconductor devices that includes forming a local interconnection layer on the substrate, covering both the active region and groove isolation regions, and using a patterned hard mask to etch the layer, allowing for reduced distances between gate structures and isolation regions, thereby enabling miniaturization beyond conventional limitations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If advanced reticle technologies are used to reduce distances between gate and isolation regions, then device density increases, but manufacturing cost increases significantly
Solution Approach 1:
The patent divides the interconnection structure into global interconnection layers and local interconnection layers. The local interconnection layers are formed in specific regions between gate structures and isolation regions, allowing selective reduction of distances only where needed, rather than requiring advanced reticle technologies for the entire device structure.
Solution Approach 2:
The patent applies different interconnection layer configurations to different regions of the device. Local interconnection layers are formed specifically in regions where distance reduction is needed, while other regions maintain conventional structures. This localized approach enables density improvement without requiring costly advanced reticle technologies across the entire manufacturing process.
2Productivity
If spacer lateral size is reduced to increase device density, then more devices fit in given area, but gate current leakage increases
Solution Approach 1:
The patent introduces local interconnection layers as intermediary structures between the gate and isolation regions. These local interconnection layers serve as mediators that allow the spacer dimensions to be reduced for higher density while the local interconnection layers compensate for potential leakage issues by providing controlled electrical pathways.
Solution Approach 2:
The patent adds vertical dimensionality to the interconnection structure by forming local interconnection layers at different heights and positions. Instead of solely relying on horizontal spacer dimensions, the solution utilizes the third dimension (vertical stacking and local layer formation) to achieve density improvement without compromising spacer integrity and gate leakage performance.
3Productivity
If contact hole dimensions are reduced to increase device density, then more contacts per area, but manufacturing precision requirements increase
Solution Approach 1:
The patent segments the interconnection architecture into multiple layers including local interconnection layers that can be formed with relaxed dimensional constraints. This segmentation allows the contact structure to be distributed across different layers and regions, reducing the precision requirements for individual contact holes while maintaining overall high device density.
Solution Approach 2:
The patent utilizes vertical stacking of interconnection layers to increase the number of interconnections per unit area. Instead of solely increasing contact hole density in the planar dimension, the solution adds contacts in the vertical dimension through multiple interconnection layers, thereby achieving higher density without proportionally increasing the manufacturing precision requirements for each individual contact hole.
Data Source
AI summary
A semiconductor device and method of manufacturing the semiconductor device are disclosed. The semiconductor device includes: a substrate including an active region and at least one groove isolation region formed on the substrate, wherein the at least one groove isolation region is formed adjoining the active region, a gate structure formed on a first portion of the active region, and at least one local interconnection layer formed on a portion of the substrate, wherein the at least one local interconnection layer is located on a side of the gate structure, and covers at least a second portion of the active region and a portion of the groove isolation region adjoining the active region.