Local Vertical Interconnects for Dense Monolithic Stack Transistors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor technologies face challenges in increasing integration density and flexibility in stacked transistors, particularly in achieving functional interconnections between transistors on different layers, which limits the combined functionality and requires complex vertical connections that are difficult to execute.
Innovation Solution
A method for forming stacked transistors involves creating a sacrificial cap over a lower level transistor's interconnect, forming an upper level transistor, removing the sacrificial cap to create an opening, and forming a local vertical interconnect in direct contact with the lower level interconnect, enabling flexible and heterogeneous integration of transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple stacked layers of transistors are produced to increase integration density, then the integration density of transistors is improved, but the complexity of vertical connections between layers increases
Solution Approach 1:
A sacrificial cap layer is introduced as an intermediary element during the fabrication process. This sacrificial cap is formed over the lower level transistor interconnect, allowing the upper level transistor to be fabricated separately. The sacrificial cap is then removed to create an opening that enables direct contact between the upper level interconnect and lower level interconnect, simplifying the vertical connection process while maintaining high integration density.
2Adaptability or versatility
If complex vertical connections are used to connect transistors on different layers, then interlayer connectivity is achieved, but the ease of manufacture deteriorates
Solution Approach 1:
The sacrificial cap is formed in advance during the lower level transistor fabrication process, before the upper level transistor is created. This preliminary action establishes a predefined pathway for future vertical interconnection. When the upper level transistor is fabricated and the sacrificial cap is removed, the opening is already prepared, making the vertical connection process straightforward and manufacturable.
Solution Approach 2:
The sacrificial cap serves as a temporary intermediary structure that facilitates the fabrication process. It allows the upper level transistor to be formed with proper alignment and spacing, then is removed to create the vertical interconnect opening. This intermediary approach simplifies the overall manufacturing process compared to attempting to create complex vertical connections directly.
3Adaptability or versatility
If direct vertical interconnects are formed between upper and lower level transistors, then functional interconnections are enabled, but the manufacturing precision requirements increase
Solution Approach 1:
The sacrificial cap acts as a precision-guided intermediary that defines the exact location and dimensions of the future vertical interconnect opening. By forming the sacrificial cap with controlled dimensions and position during the lower level fabrication, the subsequent opening creation process achieves high precision alignment between upper and lower level interconnects without requiring complex alignment procedures.
Solution Approach 2:
The sacrificial cap is formed in advance with precise dimensions and positioning, establishing a template for the vertical interconnect. This preliminary structuring of the interconnect pathway before upper level fabrication allows for controlled and precise vertical connections, reducing the precision requirements during later alignment-critical steps.
Data Source
AI summary
A method for forming a stacked transistor includes forming a sacrificial cap over a first interconnect of a lower level transistor. The method further includes forming an upper level transistor above the sacrificial cap. The method further includes removing the sacrificial cap to form an opening such that the opening is delimited by the upper level transistor. The method further includes forming a second interconnect in the opening such that the second interconnect is in direct contact with the first interconnect.