Local X-Decoder Well Disturb Prevention in NOR Flash
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Solution Overview
Problem
NOR flash memory systems experience well disturb failures and gate-induced drain leakage due to unselected word lines during erase mode, leading to unintended bit changes and damage to the local X-decoder.
Innovation Solution
A local X-decoder with an unselected erase detecting unit that increases the absolute voltage coupled to the word line signal from the well of the memory cell during erase mode, ensuring the word line signal floats to the same level as the well when unselected, and a voltage clamping transistor to reduce the voltage difference across the gate oxide, thereby preventing well disturb failures and damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the local X-decoder operates in erase mode with unselected word lines, then the erase function can be performed, but well disturb failures occur causing programmed bits to unintentionally become erased bits
Solution Approach 1:
The patent applies preliminary anti-action by proactively counteracting the well disturb effect before it can cause damage. The unselected word line voltage is actively managed to prevent the electric field buildup that would otherwise occur during erase mode operation. This is achieved through circuitry that monitors and adjusts voltages to preemptively neutralize the harmful well disturb effect, thereby protecting programmed bits from unintentional erasure.
Solution Approach 2:
The patent implements parameter changes by dynamically adjusting voltage levels during erase mode operation. Specifically, the unselected word line voltage is modified to float at the same level as the well potential, preventing the voltage differential that causes well disturb. This parameter adjustment transforms the operating conditions to eliminate the harmful effect while maintaining erase functionality.
2Productivity
If the unselected word line voltage is maintained during erase mode, then the erase operation can proceed, but gate induced drain leakage increases causing damage to the local X-decoder
Solution Approach 1:
The patent applies parameter changes by modifying the voltage parameters of unselected word lines during erase mode. The voltage is adjusted to float at the well potential level, which reduces the voltage difference across the gate oxide of transistors in the local X-decoder. This parameter adjustment significantly reduces gate induced drain leakage while maintaining the erase operation's productivity.
Solution Approach 2:
The patent converts the potentially harmful high voltage condition into a beneficial state by allowing the unselected word line to float at the well potential. This transformation reduces the voltage stress on the decoder transistors, converting what would be a damaging high-field condition into a protective low-stress state that prevents GIDL damage while maintaining erase functionality.
Data Source
AI summary
A local X-decoder for a memory system includes a decoding unit configured to generate a word line signal to a memory cell of a memory array of the memory system; and an unselected erase detecting unit coupled to the decoding unit, and configured to increase an absolute voltage coupled to the word line signal from a well of the memory cell according to an unselected erase mode signal generated by an erase mode decoder of the memory system; wherein the word line signal is floating to a same level as the well of the memory cell when the memory cell is unselected in an erase mode of the memory system.