Localized Energy Surface Planarization for Semiconductor Wafer Etching
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Solution Overview
Problem
Current surface planarization processes in semiconductor manufacturing, particularly 'stop-on' layers, require complex multi-stage CMP processes including bulk removal and overpolishing, which are difficult to control and prone to errors like erosion and dishing, necessitating expensive post-CMP corrections.
Innovation Solution
A novel surface planarization method using localized selective etching, where the remaining layer thickness is mapped and external energy distribution is applied to control etch rates across the wafer, eliminating the need for overpolishing and buffing stages by precisely removing material based on varying etch rates defined by temperature patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multi-stage CMP process (bulk removal + overpolishing) is used for stop-on layer planarization, then material removal completeness is improved, but process complexity and control difficulty increase
Solution Approach 1:
The patent extracts and removes the stop layer completely in a single CMP stage using optimized slurry and process parameters, eliminating the need for the separate overpolishing stage. This extraction of the stop layer function simplifies the overall process while maintaining complete material removal.
Solution Approach 2:
The patent performs preliminary optimization of CMP parameters (slurry composition, downforce, rotation speed) before the main planarization process to ensure that the stop layer can be completely removed in one pass. This preliminary preparation prevents the need for subsequent overpolishing stages.
2Manufacturing precision
If multi-stage CMP process is used, then planarization quality is improved, but processing time increases
Solution Approach 1:
The patent performs preliminary optimization of CMP parameters to ensure complete stop layer removal in a single stage, eliminating the time-consuming overpolishing and buffing stages that follow in conventional multi-stage processes.
Solution Approach 2:
The patent maintains continuous planarization action in a single uninterrupted CMP stage, avoiding the interruption and repositioning required between multiple stages. This continuous process maintains quality while reducing total processing time.
3Loss of substance
If conventional CMP process is used, then material removal is achieved, but erosion and dishing occur
Solution Approach 1:
The patent changes key CMP parameters including slurry composition (pH, particle size distribution, chemical additives), downforce pressure, and rotation speed to optimize the material removal mechanism. These parameter changes enable effective material removal while minimizing erosive and dishing effects.
Solution Approach 2:
The patent uses a composite slurry system containing multiple particle sizes and chemical additives that work synergistically. The composite nature of the slurry allows for controlled material removal with reduced harmful effects compared to single-component slurries.
4Manufacturing precision
If multiple CMP stages are used, then complete layer removal is ensured, but post-CMP cleaning complexity increases
Solution Approach 1:
The patent extracts and removes the stop layer completely in a single CMP stage, eliminating residual materials that would require complex post-CMP cleaning. This complete extraction in one stage simplifies the cleaning process significantly.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the planarization process, improves within-wafer uniformity and flatness, reduces post-CMP cleaning complexity, and enhances CMP tool performance by eliminating the need for multiple stages, thereby reducing costs and increasing productivity.
Implementation Method 1
an external energy source for generating a localized energy distribution within a processing region
Implementation Method 2
create, by said localized energy distribution, a predetermined temperature pattern within said processing region such that different locations of said processing region are subjected to different temperatures
Implementation Method 3
the temperature pattern at different locations of the sample's surface creates different material removal rates by said etching material composition
Data Source
AI summary
A surface planarization system is presented. The system comprises an external energy source for generating a localized energy distribution within a processing region, and a control unit for operating the external energy source to create, by the localized energy distribution, a predetermined temperature pattern within the processing region such that different locations of the processing region are subjected to different temperatures. This provides that when a sample (e.g. semiconductor wafer) during its interaction with an etching material composition is located in the processing region, the temperature pattern at different locations of the sample's surface creates different material removal rates by the etching material composition (different etch rates).