Lock Detecting Circuit for Accurate Internal Clock Phase Detection
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Solution Overview
Problem
Existing synchronous memory devices face challenges in accurately detecting the lock state of internal clocks, which affects data input/output operations, due to inefficiencies in phase detection and signal generation in feedback devices like PLL and DLL.
Innovation Solution
A lock detecting circuit is introduced, comprising a pre-clock detection signal generating circuit, a clock detection signal generating circuit, and a lock control circuit, which adjusts pulse widths and detects phase differences between clocks to generate a lock signal, using a division control circuit to initiate and manage lock detection periods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional phase detection method is used in feedback devices, then the device structure is simple, but the lock detection accuracy is insufficient
Solution Approach 1:
The lock detection circuit is divided into multiple functional modules: pre-clock detection signal generating circuit, clock detection signal generating circuit, and lock control circuit. Each module performs a specific function in the phase detection process, enabling accurate lock detection through coordinated operation of segmented components rather than a single complex circuit
Solution Approach 2:
The pre-clock detection signal generating circuit performs preliminary phase detection by generating pre-clock detection signals before final lock determination. This preliminary action allows the system to prepare detection data in advance, improving the accuracy of subsequent lock detection without adding complex real-time processing requirements
2Measurement precision
If pulse width adjustment is performed for clock detection signals, then the phase difference detection accuracy is improved, but the signal processing time increases
Solution Approach 1:
The lock control circuit operates in periodic lock detection periods, during which pulse width adjustment and phase difference detection are performed. By confining these time-consuming operations to periodic intervals rather than continuous operation, the system achieves accurate phase detection while minimizing overall time loss through efficient use of detection windows
Data Source
AI summary
A lock detecting circuit includes a pre-clock detection signal generating circuit configured to detect phases of a first clock and a second clock to generate a first pre-clock detection signal and a second pre-clock detection signal based on the detected phases, a first clock detection signal generating circuit configured to generate a first clock detection signal by adjusting a pulse width of the first pre-clock detection signal, a second clock detection signal generating circuit configured to generate a second clock detection signal by adjusting a pulse width of the second pre-clock detection signal, and a lock control circuit configured to detect a phase difference between the first clock and the second clock, based on the first clock detection signal and the second clock detection signal to generate a lock signal.