Lock and Key Through-Via Method for 3D Wafer Integration
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Solution Overview
Problem
Current 3D integration techniques face challenges in achieving high-density vertical interconnects due to limitations in deep silicon via formation and filling, alignment accuracy, and mechanical bonding strength, which restricts the advancement of microprocessor performance beyond Moore's law.
Innovation Solution
The approach involves forming shorter through vias that are exposed and filled after device layer joining, utilizing a lock and key mechanism for self-alignment, and enhancing mechanical integrity with conductive fill materials and suitable adhesives, allowing for higher via density and robust bonding without relying on deep silicon etch and fill processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If deep silicon via formation and filling processes are used, then vertical interconnect depth is increased, but manufacturing complexity and difficulty increase
Solution Approach 1:
The via formation process is segmented into two stages: first forming shallow vias through the first substrate before bonding, then completing the through-via formation after bonding by removing sacrificial material and filling. This segmentation avoids the complexity of forming deep vias through thick substrates while achieving the same vertical interconnect depth.
Solution Approach 2:
Shallow vias are formed preliminarily through the first substrate before the bonding step, and sacrificial material is deposited in advance in the second substrate. This preliminary action simplifies the overall process by avoiding the need to form deep vias through the combined thickness of both substrates after bonding.
2Manufacturing precision
If through vias are formed before wafer bonding, then alignment is simplified, but via depth requirements increase
Solution Approach 1:
The via formation is segmented into shallow vias formed before bonding and deep via completion after bonding. The pre-bonding shallow vias provide alignment references that are easier to manufacture with standard equipment, while the post-bonding completion achieves the required total depth without increasing pre-bonding via depth requirements.
3Quantity of substance
If higher via density is implemented, then interconnect capacity increases, but mechanical bonding strength decreases
Solution Approach 1:
Different regions of the wafer interface have different properties: regions with through-vias have high interconnect density, while regions with adhesive-only areas provide mechanical bonding strength. The adhesive is selectively applied to bypass areas where it can provide mechanical reinforcement without interfering with electrical connections in via regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables higher via density, improved alignment, and enhanced mechanical integrity, facilitating the stacking of multiple device layers with increased interconnect density and performance, overcoming limitations of traditional 3D integration techniques.
Implementation Method 1
The via openings are then filled with a conductive material, such as tungsten, copper, aluminum, or any other suitable conductive material, using any suitable deposition technique.
Implementation Method 2
An adhesive layer, such as a spin-on-glass adhesive, polyimide adhesive, or any other suitable adhesive, is then applied to the device layer
Data Source
AI summary
A three dimensional device stack structure comprises two or more active device and interconnect layers further connected together using through substrate vias. Methods of forming the three dimensional device stack structure comprise alignment, bonding by lamination, thinning and post thinning processing. The via features enable the retention of alignment through the lamination process and any subsequent process steps thus achieving a mechanically more robust stack structure compared to the prior art.