Lockstep Comparator Circuits for 8-Cycle Online Diagnostics
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Solution Overview
Problem
Existing lockstep testing implementations are intrusive, slow, and unable to isolate fault conditions in lockstep hardware, requiring offline testing and lacking the ability to provide comprehensive debug information for fault analysis.
Innovation Solution
The implementation of lockstep comparators that allow online testing of lockstep functionality, using two or more lockstep comparators to perform diagnostic tests while the lockstep hardware is operational, reducing test time from thousands of clock cycles to 8 cycles and providing comprehensive debug information.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional offline lockstep testing is performed, then fault detection capability is provided, but system operational time is lost and testing is intrusive
Solution Approach 1:
The patent implements preliminary action by incorporating dedicated test modes and diagnostic circuits that prepare the lockstep system for fault detection during normal operation. The system pre-configures multiple comparators and test pathways that can be activated without interrupting the primary lockstep functionality, allowing faults to be detected while the system remains operational.
Solution Approach 2:
The patent uses intermediary elements such as dedicated test control circuits and multiple comparator units that mediate between the lockstep hardware and the testing process. These intermediaries enable diagnostic operations to occur concurrently with normal operation by providing separate pathways for test signals and data flow, thus preventing intrusion into the primary operational mode.
2Reliability
If traditional lockstep testing is performed, then faults are detected, but test speed is slow requiring thousands of clock cycles
Solution Approach 1:
The patent applies segmentation by dividing the fault detection function into multiple parallel comparator units, each capable of independently testing specific aspects of the lockstep hardware. This segmentation allows the testing process to be distributed across multiple concurrent operations rather than sequential execution, dramatically reducing the total test time from thousands of clock cycles to just 8 cycles.
Solution Approach 2:
The patent implements partial action by using multiple comparators to perform different aspects of the diagnostic test simultaneously. Rather than one comparator performing all tests sequentially, each comparator performs a portion of the testing in parallel, providing excessive testing capability that ensures comprehensive fault detection while minimizing test duration.
3Reliability
If traditional lockstep testing is performed, then testing is conducted, but comprehensive debug information cannot be obtained for fault analysis
Solution Approach 1:
The patent implements feedback mechanisms where each comparator unit provides detailed output signals about its comparison results, and these results are aggregated and analyzed by control logic. The system continuously monitors and reports on the state of each comparator and the overall lockstep functionality, providing comprehensive debug information that enables precise fault localization and analysis without losing diagnostic data.
Data Source
AI summary
Lockstep comparators and related methods are described. An example apparatus includes self-test logic circuitry having first outputs, and comparator logic including selection logic having first inputs and second outputs, ones of the first inputs coupled to the first outputs, first detection logic having second inputs and third outputs, the second inputs coupled to the second outputs, second detection logic having third inputs and fourth outputs, the third inputs coupled to the third outputs, latch logic having fifth inputs and fifth outputs, the third output and the fourth output coupled to the fifth inputs, and error detection logic having sixth inputs coupled to the fifth inputs.