Dual-Core Lockstep Microcontroller Comparator Fault Detection
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Solution Overview
Problem
Existing microcontrollers in safety-focused applications face challenges with software-based diagnostic self-tests that consume resources, provide limited diagnostic coverage, and have high fault detection time intervals, especially in detecting timing-related errors.
Innovation Solution
A dual core lockstep microcontroller apparatus with hardware-based fault detection using parallel processing, comparators, logic gates, and error injection circuits to enhance fault detection and achieve rapid recovery to a safe state.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If software-based diagnostic self-tests are used, then fault detection capability is provided, but fault detection time interval increases and diagnostic coverage is limited
Solution Approach 1:
The patent replaces software-based diagnostic self-tests with a hardware-based fault detection system using comparators and logic gates. The comparator circuitry continuously compares outputs from multiple central processing circuitries in real-time, enabling hardware-level fault detection that operates independently of software execution cycles, thereby reducing fault detection time intervals and improving diagnostic coverage for timing-related errors.
Solution Approach 2:
The hardware fault detection system operates continuously and concurrently with the central processing circuitries executing instructions. The comparator circuitry maintains continuous comparison of outputs from multiple processing units, ensuring that faults are detected immediately when they occur, rather than relying on periodic software-based diagnostic cycles that interrupt normal operation.
2Reliability
If software-based diagnostic self-tests are used, then fault detection capability is provided, but resource consumption increases
Solution Approach 1:
The patent replaces resource-intensive software-based diagnostic self-tests with dedicated hardware comparator circuitry that operates at the electrical signal level. This hardware approach eliminates the need for software implementation, reducing CPU resource consumption and energy usage while providing continuous fault detection capability through purely electrical comparisons of output signals from multiple processing units.
3Device complexity
If single core processing is used, then device complexity is reduced, but fault detection capability is limited
Solution Approach 1:
The patent divides the processing system into multiple independent central processing circuitries that execute instructions in parallel. Each processing unit has its own output that is fed to the comparator circuitry, enabling independent fault detection for each core. This segmentation allows the system to maintain relatively simple individual processing units while achieving enhanced fault detection capability through parallel architecture and hardware-based comparison.
Data Source
AI summary
A method for fault detection in a dual core lockstep microcontroller is provided. The method may include executing a set of instructions by a first central processing circuitry, executing the set of instructions by one or more second central processing circuitries operating in parallel with the first central processing circuitry, comparing an output from the first central processing circuitry with an output from one or more second central processing circuitries using a first comparator, comparing the output from the first central processing circuitry with the output from the one or more second central processing circuitries using one or more second comparators, and triggering, by at least one logic gate, a fault signal in response to output signals received from the first comparator and the one or more second comparators.