Low Voltage Logic Circuit Current Balancing
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Solution Overview
Problem
The increasing power dissipation in microprocessors due to low voltage CMOS processes leads to high current requirements, which are limited by parasitic resistance in chip packaging and printed circuit boards, making it difficult to reduce voltage drop without increasing material and processing costs.
Innovation Solution
A circuit comprising a current balancing module that connects modules in series between reference potentials, using a buck converter, 2:1 DC/DC converter, balanced switched capacitance device, or linear push-pull regulator to balance current consumption between modules, reducing the difference in current levels and voltage drop.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If low voltage CMOS processes are used to increase processing power, then device integration and computing capability improve, but current requirements increase leading to excessive power dissipation
Solution Approach 1:
The patent changes the voltage parameter from low voltage (1V or below) to higher voltage (above 1V) operation. By operating at higher voltage levels, the system reduces current requirements while maintaining the same power delivery capability, thereby reducing power dissipation in parasitic resistances of packaging and PCB traces
2Loss of energy
If supply voltage is increased to reduce current levels, then power dissipation in parasitic resistance decreases, but voltage drop across parasitic resistance increases
Solution Approach 1:
The patent segments the power delivery path into multiple series-connected voltage domains. Each domain operates at a different voltage level, with higher voltages used in regions with higher parasitic resistance (packaging, PCB) and lower voltages used at the chip level. This segmentation allows optimization of current levels at each segment to minimize overall power dissipation while maintaining adequate voltage margins
3Reliability
If more bond wires are used to reduce power supply resistance, then parasitic resistance decreases, but packaging complexity and cost increase
Solution Approach 1:
The patent changes the operating voltage parameter to compensate for fixed parasitic resistances. Instead of attempting to reduce parasitic resistance through increased bond wire count (which increases complexity), the system operates at higher voltages where the fixed voltage drop becomes a smaller proportion of the total supply voltage, thereby maintaining adequate voltage margins without additional packaging complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution allows for efficient operation of low voltage complex logic macros at higher voltage levels with lower current levels, reducing parasitic resistance and power dissipation while maintaining system performance.
Implementation Method 1
A current balancing module communicates with a node between the first and second modules and reduces a difference in current consumption between the first and second modules. The current balancing module comprises a buck converter.
Implementation Method 2
An inductance element communicates with the conduction and freewheeling switches and the node
Implementation Method 3
A capacitance element communicates with the fourth reference potential and the node
Implementation Method 4
A conduction switch that communicates with a third reference potential. A freewheeling switch communicates with a fourth reference potential and the conduction switch
Data Source
AI summary
A circuit comprises 2n modules that are connected in series between first and second reference potentials. 2n−1 nodes that are arranged between adjacent ones of said 2n modules. 2n−1 2:1 DC/DC converters, wherein each of said 2n−1 2:1 DC/DC converters communicates with a respective one of said 2n−1 nodes.