Programmable Logic Circuit With Serial Functional Block Execution
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Solution Overview
Problem
Current systems for controlling nuclear facilities require frequent reprogramming and requalification of FPGA circuits, which are resource-intensive and demand significant expertise, especially when control command applications change, and they struggle to meet deterministic safety demands efficiently.
Innovation Solution
A programmable logic circuit with a single functional block of each type, allowing these blocks to be executed in series, reducing the number of logic resources and energy consumption while ensuring deterministic control through a single execution cycle, and incorporating features like finite-state machines and parallelizable floating-point units for efficient data processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multiple functional blocks of the same type are implemented in parallel in FPGA, then the control command application can be executed faster, but the number of logic resources increases and the device complexity increases
Solution Approach 1:
The patent segments the control command application into multiple successive execution cycles, where each cycle executes a subset of functional blocks. This temporal segmentation replaces spatial parallelism with sequential processing, reducing the number of simultaneous logic resources required while maintaining execution completeness.
Solution Approach 2:
The patent implements periodic action by executing functional blocks in successive cycles with regular time intervals. Each cycle processes a portion of the control command application, and the periodic repetition of cycles ensures complete execution while allowing logic resources to be reused across cycles rather than duplicated.
2Productivity
If functional blocks are executed in parallel across multiple successive cycles, then the control command application can be completed, but synchronization requirements increase the device complexity and deterministic safety demonstration becomes more difficult
Solution Approach 1:
The patent applies preliminary action by pre-defining the execution sequence and timing of functional blocks before runtime. The execution order and cycle timing are determined in advance, eliminating the need for complex runtime synchronization mechanisms and making deterministic behavior verifiable through static analysis.
Solution Approach 2:
The patent enables self-service by designing the execution module to automatically manage the successive cycles and functional block execution without requiring external synchronization intervention. The system self-regulates the timing and sequencing, reducing the complexity of external synchronization control while maintaining deterministic execution.
3Productivity
If a large number of functional blocks of the same type are implemented, then the control command application can be executed in parallel cycles, but the energy consumption increases
Solution Approach 1:
The patent merges the execution of multiple functional blocks into successive cycles, where the same logic resources are reused across cycles rather than being duplicated in parallel. This consolidation reduces the total number of active logic elements at any given time, thereby reducing energy consumption while maintaining productivity through temporal multiplexing.
4Reliability
If time delays are implemented for synchronization between cycles, then deterministic control is achieved, but the loss of time increases
Solution Approach 1:
The patent maintains continuity of useful action by ensuring that functional blocks are continuously executed across successive cycles without idle gaps. The time delays are minimized and integrated into the continuous execution flow, allowing the system to maintain deterministic control while maximizing the utilization of execution time for productive work rather than waiting.
Data Source
AI summary
A programmable logic circuit (10) for controlling an electrical facility, in particular a nuclear facility, includes an operating unit (14). The operating unit includes a plurality of types of functional blocks (FB1, FBi, FBN), two distinct types of functional blocks being suitable for executing at least one distinct function, at least one processing module suitable for receiving at least one sequence (46) of functional block(s) to be executed, and at least one internal memory (38) configured to store at least said sequence (46). The programmable logic circuit (10) includes a single functional block of each type, a given functional block being suitable for being called several times, and an execution module (22) configured to execute the called functional block(s) in series, according to said sequence (46).