Constant-Hamming-Weight Logic Circuit for Stable Power Use
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Solution Overview
Problem
The increasing electrical power consumption in semiconductor devices due to advancements in LSI technology leads to heat generation and reduced battery operation time, necessitating a solution to stabilize power consumption fluctuations during data processing.
Innovation Solution
A logic circuit design incorporating a decoder, interconnect network, and encoder that converts binary input data into bit data with a constant Hamming weight, allowing for bit pattern substitution and stabilization of electrical power consumption by maintaining a consistent number of active signals regardless of input data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If binary input data is directly processed by conventional logic circuits, then data processing speed is maintained, but electrical power consumption fluctuates greatly in response to changes in simultaneously processed data
Solution Approach 1:
The logic circuit is segmented into three functional modules: a decoder that converts binary input data into bit data with constant Hamming weight, an interconnect network that performs bit pattern substitution, and an encoder that converts the processed bit data back to binary output data. This segmentation allows each module to perform a specific function in the power stabilization process.
Solution Approach 2:
The decoder and encoder act as intermediary components between the input and output of the logic circuit. The decoder transforms variable-Hamming-weight binary data into constant-Hamming-weight bit data, and the encoder performs the reverse transformation, thereby mediating the power consumption fluctuations while preserving the computational functionality through the interconnect network.
2Reliability
If power circuit design considers maximum and minimum power consumption values, then power fluctuation is accounted for, but design complexity and conservatism increase
Solution Approach 1:
The decoder performs preliminary action by converting the input binary data into bit data with constant Hamming weight before the data enters the main processing logic. This preliminary transformation ensures that all subsequent processing operates on data with uniform power consumption characteristics, eliminating the need for conservative design margins based on maximum/minimum power variations.
Solution Approach 2:
The invention changes the parameter of Hamming weight from variable to constant through the decoder transformation. By transforming the data representation from binary form (with variable population count) to a form with constant population count, the power consumption parameter becomes stable regardless of the input data pattern.
3Productivity
If high-performance LSI technology is used, then processing capability is improved, but electrical power consumption and heat generation increase
Solution Approach 1:
The invention applies local quality by maintaining constant Hamming weight specifically in the data paths that contribute to power consumption, while allowing the overall system to utilize high-performance LSI technology for processing. The constant-weight property is applied locally to the bit data representation, enabling high-performance processing with stabilized power characteristics.
Data Source
AI summary
A logic circuit that executes a prescribed arithmetic processing includes a decoder that converts one or more binary input data into a first plurality of bit data of a constant hamming weight regardless of a hamming weight of the input data, an interconnect network that is connected to the decoder, changes a bit pattern of the first plurality of bit data and generates a second plurality of bit data, according to receiving the first plurality of bit data converted according to the decoder, and substituting a bit position of the received first plurality of bit data for the purpose of the prescribed arithmetic operation, and an encoder connected to the interconnect network and converts the second plurality of bit data generated in the interconnect network into one or more binary output data.