Logic Circuit Clock Jitter for Anti-Correlation Attack Protection
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Solution Overview
Problem
Integrated circuits are susceptible to active attacks that analyze voltage contrasts and logic states by correlating clock edges, making it difficult to protect internal functions from reverse engineering.
Innovation Solution
A system with a clock that includes a fixed clock component and a jitter clock component, generating a non-deterministic clock edge to obscure the timing of logic operations, making it difficult for attackers to synchronize X-ray analysis with clock edges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a deterministic clock signal is used to drive logic circuits, then the circuit operation is stable and predictable, but the timing of logic operations becomes vulnerable to correlation analysis in active attacks
Solution Approach 1:
The patent applies dynamics by transitioning from a static, deterministic clock signal to a dynamic, non-deterministic clock signal with random edge variations. The clock generator introduces random jitter to the clock edges, making the timing unpredictable while maintaining functional operation. This dynamic approach prevents attackers from correlating specific clock edges with logic operations, thereby protecting against active attacks while preserving circuit reliability.
Solution Approach 2:
The patent changes the temporal parameters of the clock signal by introducing random variations in edge timing. Instead of using a fixed, predictable clock period and phase, the system modifies the clock signal's timing parameters through random jitter injection. This parameter change disrupts the deterministic relationship between clock edges and logic operations, making reverse engineering through timing analysis ineffective while maintaining operational stability.
2Object-affected harmful factors
If clock edges are made non-deterministic to prevent correlation analysis, then protection against active attacks is improved, but the precision of timing-based measurements deteriorates
Solution Approach 1:
The patent segments the clock signal generation into two independent parts: a deterministic base clock signal and a random jitter component. The base clock maintains stable frequency and phase for normal operation, while the random jitter component is added separately to create non-deterministic edge timing. This segmentation allows the system to achieve protection against reverse engineering without completely sacrificing timing precision, as the base clock structure remains intact.
Solution Approach 2:
The patent introduces a random jitter generator as an intermediary component between the deterministic clock source and the logic circuit. This intermediary adds random variations to the clock edges, preventing direct correlation between clock signals and logic operations. The intermediary preserves the fundamental clock structure while obscuring precise timing relationships, thereby protecting against measurement-based attacks without entirely eliminating timing functionality.
Data Source
AI summary
Embodiments of the disclosure provide systems and methods to operate a logic circuit with non-deterministic clock edge variations. A system may include a clock coupled to a logic circuit, the logic circuit having a set of source latches coupled to a set of capture latches through a set of logic cones. The clock includes a fixed clock component configured to generate a clock signal having a first clock edge, and a jitter clock component coupled to the fixed clock component and configured to modify the clock signal to have a second clock edge based on a non-deterministic value. The clock transmits the clock signal with the second clock edge to drive the set of source latches and the set of capture latches of the logic circuit. A clock controller coupled to the jitter clock component generates the non-deterministic value.