Logic-Embedded Diode Coupled to Floating Gate for Power Gating Retention
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Solution Overview
Problem
Current integrated circuit technologies face challenges in retaining logic states during power gating due to high leakage power and the inefficiency of existing non-volatile memory solutions, particularly at sub-10 nm scales, where variability in fabrication processes limits further scaling and introduces complexity and high write power consumption.
Innovation Solution
The integration of a logic-embedded diode/tunnel diode coupled to a floating gate, which utilizes a diode portion over the source or drain of memory transistors to conduct charge for state retention during power gating, enabling improved write voltage vs retention time trade-offs and reducing leakage power, without requiring special memory-specific processing steps or additional voltage rails.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used for scaling, then manufacturing simplicity is maintained, but manufacturing precision deteriorates at sub-10 nm range
Solution Approach 1:
The patent merges logic transistors and memory transistors into a unified structure where logic transistors have their source/drain regions serve dual functions as both logic device terminals and memory device electrodes. This integration allows simultaneous achievement of high precision at sub-10 nm scale and process simplicity by using a single fabrication process for both logic and memory functions.
Solution Approach 2:
The source and drain regions of the logic transistor are designed to serve multiple functions: they act as logic device terminals for logic operation and simultaneously serve as control electrode and storage electrode for the memory device. This multi-functionality enables precise feature control at sub-10 nm while avoiding the need for separate memory-specific processing steps.
2Loss of energy
If power gating is implemented to reduce leakage power, then energy consumption is reduced, but logic state retention becomes problematic
Solution Approach 1:
Before power gating is activated to reduce leakage power, the patent performs preliminary action by transferring the logic state to the memory device through charge pumping between the logic transistor and memory transistor. This preliminary charge transfer ensures that logic states are preserved in the memory device before power is removed, preventing information loss during power gating.
Solution Approach 2:
The patent introduces a memory device as an intermediary between the logic transistor and power gating mechanism. The memory device acts as a mediator that stores the logic state during power gating, enabling leakage power reduction without logic state loss. The coupled structure of logic and memory transistors facilitates this intermediary function through direct charge transfer.
3Loss of information
If existing non-volatile memory solutions are used for state retention, then logic state retention is achieved, but write power consumption increases
Solution Approach 1:
The patent combines logic and memory functions in a single coupled transistor structure, eliminating the need for separate memory devices with high write power consumption. The integrated structure allows logic states to be transferred to and retained by the memory transistor using minimal additional power, achieving state retention with significantly reduced write power compared to conventional non-volatile memory solutions.
4Quantity of substance
If feature scaling continues to increase density, then device capacity increases, but fabrication variability worsens
Solution Approach 1:
By merging logic and memory transistors into a single integrated structure with shared source/drain regions, the patent reduces the total number of fabrication steps and process variations. This unified approach maintains manufacturing precision at high device densities by avoiding the accumulation of variability from multiple separate processing sequences.
Solution Approach 2:
The multi-functional source/drain regions that serve both logic and memory purposes reduce the number of distinct features that must be precisely fabricated. This universality simplifies the fabrication process at sub-10 nm scale, reducing process variability while maintaining high device density through efficient space utilization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces leakage power, enables fast save-restore times, and provides a low-cost, simple integration with high-performance logic, allowing for efficient logic state retention even at low voltages, thus overcoming the limitations of existing technologies.
Implementation Method 1
A diode portion is formed over one of the source and the drain of at least one of the memory transistors to conduct charge to the floating-gate of the at least one of the memory transistors
Implementation Method 2
A logic-embedded diode/tunnel diode coupled to a floating gate with I-V characteristics suitable for logic state retention
Data Source
AI summary
An integrated circuit structure comprises a substrate having a memory region of and an adjacent logic region. A first N type well (Nwell) is formed in the substrate for the memory region and a second Nwell formed in the substrate for the logic region. A plurality of memory transistors in the memory region and a plurality of logic transistors are in the logic region, wherein ones the memory transistors include a floating gate over a channel, and a source and a drain on opposite sides of the channel. A diode portion is formed over one of the source and the drain of at least one of the memory transistors to conduct charge to the floating-gate of the at least one of the memory transistors for state retention during power gating.