Reconfigurable Logic Fabric With On-Chip Nonvolatile Routing Control

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Solution Overview

Problem

Existing reconfigurable logic devices require external memory devices for operation, making real-time reconfiguration difficult and increasing device size and manufacturing costs.

Innovation Solution

Incorporating nonvolatile memory devices within the logic device to control wire connections between logic blocks, allowing for real-time reconfiguration without the need for external memory, by using global and local wire connection units and controllers to program and control the connections between wires.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If external memory devices are used to control wire connections in reconfigurable logic devices, then the device can store configuration data, but the device size and manufacturing costs increase

Engineering Contradiction:
Improvedevice sizeVSAvoidreconfiguration capability
Core Design Contradiction:
Quantity of substanceVSAdaptability or versatility

Solution Approach 1:

The patent merges the memory function and logic device function into a single integrated structure. Non-volatile memory cells are embedded within the logic device fabric, allowing configuration data to be stored on-chip without requiring separate external memory devices. This integration eliminates the need for external memory while maintaining full reconfiguration capability.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The non-volatile memory cells serve multiple functions: they store configuration data for wire connections, retain data without external power (non-volatile), and can be programmed in real-time. This multi-functionality replaces what would traditionally require separate external memory devices while enabling real-time reconfiguration.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Productivity

If external memory devices are used for storing configuration data, then data can be retained, but real-time reconfiguration becomes difficult

Engineering Contradiction:
Improvereconfiguration speedVSAvoiddata retention
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent introduces non-volatile memory cells as an intermediary between the configuration control logic and the wire connection structure. These memory cells can be rapidly programmed to change wire connections in real-time while their non-volatile nature ensures data retention when power is removed, bridging the gap between speed and reliability requirements.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent changes the physical state or electrical characteristics of the non-volatile memory cells to represent different connection states. By programming these memory cells with different data values, the wire connections between logic blocks can be dynamically reconfigured in real-time while maintaining data retention capabilities.

Inventive Principle:
Principle #35Parameter changes

3Ease of manufacture

If external memory devices are used, then configuration data can be stored, but manufacturing costs increase

Engineering Contradiction:
Improvemanufacturing costVSAvoiddevice integration
Core Design Contradiction:
Ease of manufactureVSQuantity of substance

Solution Approach 1:

The patent combines multiple functions (logic operations and configuration data storage) into a single integrated device. By embedding non-volatile memory cells within the logic device fabric, the patent eliminates the need for separate external memory devices, reducing the total component count and manufacturing complexity while maintaining full functionality.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS8497703B2Reconfigurable logic devices
Publication Date: 2013.07.30 SAMSUNG ELECTRONICS CO LTD
  • US8497703B2 patent drawing
  • US8497703B2 patent drawing
  • US8497703B2 patent drawing

AI summary

Example embodiments provide a reconfigurable logic device including at least two logic blocks having a first logic block and a second logic block, a global wire group including at least a plurality of first global wires connected to the first logic block and a plurality of second global wires connected to the second logic block, and a global controller including a plurality of first nonvolatile memory devices associated with at least one first global wire and one second global wire, the global controller configured to selectively couple the pluralities of first and second global wires based on first data stored in the associated first nonvolatile memory devices.