Logic State Retention Circuit Using a Configurable Footer
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Solution Overview
Problem
Existing integrated circuit designs face challenges in reducing leakage current while maintaining logic state retention during power-down modes, as traditional methods either slow device speed or require additional surface area for state retention mechanisms.
Innovation Solution
A circuit utilizing a single configurable footer device that functions as a diode during power gating and a pass transistor during normal operation, reducing surface area and leakage current while retaining logic states, using a storage circuit with a power gate device and a shorting device to selectively convert the footer device's operation mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional storage mechanisms are incorporated to retain logic state during power gating, then logic state retention is achieved, but surface area on the integrated circuit significantly increases
Solution Approach 1:
The patent combines the power gating function and logic state retention function into a single flip-flop circuit structure. The footer device serves dual purposes: it acts as a power gating switch to cut off power supply while simultaneously functioning as part of the flip-flop's storage mechanism to retain logic states. This merging eliminates the need for separate additional storage mechanisms, thereby achieving logic state retention without significantly increasing surface area.
2Loss of energy
If two or more power supplies are routed to provide reduced power supply voltage to flip-flops during power gate mode, then leakage current is further reduced, but routing complexity and surface area for header/footer devices significantly increase
Solution Approach 1:
The patent implements a universal power supply routing structure where a single power supply (VDD) serves multiple functions: it provides power during normal operation mode and provides reduced power supply voltage to flip-flops during power gate mode. The footer device, when configured as a diode, automatically generates the reduced voltage level without requiring separate power supply routing. This multi-functionality approach reduces leakage current while avoiding the complexity of routing multiple power supplies and their associated header/footer devices.
3Loss of energy
If threshold voltage of transistors is increased to reduce leakage current, then leakage current is reduced, but operating speed of the device slows down
Solution Approach 1:
The patent employs dynamic threshold voltage adjustment through the footer device configuration. During power gate mode, the footer device is configured as a diode, which dynamically changes the threshold voltage of the flip-flop transistors to a higher level, thereby reducing leakage current. During normal operation mode, the footer device is configured as a pass transistor, which restores the threshold voltage to its original lower level, maintaining fast operating speed. This dynamic reconfiguration allows the circuit to optimize between leakage reduction and speed performance based on the operational mode.
Data Source
AI summary
A storage circuit has an input for receiving and storing data, a first power terminal coupled to a first conductor for receiving a first power supply voltage, and a second power terminal coupled to a second conductor. A power gate device has a first terminal coupled to the second conductor, a control terminal for receiving a bias voltage in response to a control signal, and a second terminal coupled to a terminal for receiving a second power supply voltage. A shorting device selectively electrically short circuits the first terminal of the power gate device to the control terminal of the power gate device in response to the control signal, thereby converting the power gate device from a transistor into a diode-connected device. The shorting device is smaller in size than the power gate device.