Sequential Logic Element Timing Evaluation for Setup and Hold Limits
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Solution Overview
Problem
In the design of application-specific integrated circuits (ASICs) based on standard cell libraries, evaluating the performance of sequential logic elements such as flip-flops and latches is challenging due to varying structures and MOS types, making it difficult to determine optimal setup and hold times for reliable data sampling.
Innovation Solution
A method and device that decrement the setup time of a sequential logic element from a preset value to another, recording sampled values, and calculating evaluation parameters like output delay average value, target setup time, metastable time, and hold time to effectively assess and improve the performance of the sequential logic element.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the setup time is decremented to evaluate performance, then the measurement precision of timing parameters is improved, but the stability of the sequential logic element output deteriorates
Solution Approach 1:
The patent applies preliminary action by performing multiple simulations with incrementally decreasing setup times before final evaluation. The method pre-calculates setup times through multiple simulation rounds, using the results to determine the final setup time parameter. This preliminary iterative process ensures measurement precision while maintaining output stability by identifying the optimal setup time before actual operation.
Solution Approach 2:
The patent implements dynamics by making the setup time parameter adjustable and variable during the evaluation process. The setup time is dynamically decremented in simulation steps, allowing the system to adaptively find the optimal value. This dynamic adjustment enables precise measurement of timing parameters while observing the transition point where output stability changes, resolving the contradiction between precision and stability.
2Measurement precision
If multiple simulation rounds are performed to accurately determine setup time, then the measurement precision is improved, but the productivity of the evaluation process deteriorates
Solution Approach 1:
The patent uses preliminary action by performing initial simulation rounds to establish a range for the setup time parameter before conducting final precise measurements. The first simulation round determines a preliminary setup time value, which then guides subsequent more precise simulations. This staged approach ensures accurate measurement while avoiding unnecessary computational overhead from excessive simulation rounds.
Solution Approach 2:
The patent applies partial action by performing simulations with different levels of precision at different stages. Initial simulations use coarser setup time decrements to quickly establish bounds, while final simulations use finer decrements only within the identified range. This partial application of detailed simulation only where necessary improves measurement precision while maintaining evaluation productivity.
Data Source
AI summary
A method for evaluating performance of a sequential logic element includes: inputting a preset clock signal and a data signal to a sequential logic element to be tested; decrementing a setup time of the sequential logic element from a first preset value to a second preset value based on a preset decrement step, where the first preset value is determined by a setup time when the sequential logic element to be tested outputs a target sampled value, and the second preset value is determined by a setup time when the sequential logic element outputs a reverse value of the target sampled value; and determining an evaluation parameter of the sequential logic element based on a sampled value output by the sequential logic element after each decrement of the setup time, and evaluating performance of the sequential logic element based on the evaluation parameter of the sequential logic element to be tested.