Logical IP Subnet Mapping Across L2 Fabrics for VM Migration

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Solution Overview

Problem

Existing high performance computing environments face challenges in maintaining efficient network connectivity and live migration of virtual machines due to complex addressing and routing schemes, particularly in InfiniBand networks, which hinder scalability and flexibility.

Innovation Solution

Implementing a system and method to support a single logical IP subnet across multiple independent layer 2 subnets, utilizing prepopulated LIDs in a vSwitch architecture, enabling dynamic reconfiguration and efficient routing in InfiniBand and RoCE fabrics, and providing a scalable and topology-agnostic mechanism for network reconfiguration.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multiple independent layer 2 subnets are used in high performance computing environments, then network scalability and flexibility are improved, but addressing and routing complexity increases

Engineering Contradiction:
Improvenetwork scalabilityVSAvoidaddressing and routing complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent introduces a mapping table as an intermediary data structure that stores the correspondence between layer 2 addresses (LIDs) and layer 3 addresses (IP addresses). This mapping table acts as a mediator that simplifies the addressing and routing process across multiple layer 2 subnets, allowing systems to communicate using familiar layer 3 addresses while the mapping table handles the complex layer 2 address translation in the background.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Adaptability or versatility

If virtual machines are migrated between hosts in InfiniBand networks, then resource utilization and flexibility are improved, but network connectivity and performance are degraded due to complex addressing schemes

Engineering Contradiction:
Improvelive migration capabilityVSAvoidnetwork connectivity
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent changes the addressing parameter from layer 2 addresses (LIDs) to layer 3 addresses (IP addresses) for virtual machine identification and communication. This parameter change allows virtual machines to maintain consistent IP addresses during migration between hosts, simplifying the migration process and maintaining network connectivity without the complexity of reconfiguring layer 2 addresses in InfiniBand networks.

Inventive Principle:
Principle #35Parameter changes

3Productivity

If traditional network architectures are used in cloud computing environments, then implementation simplicity is maintained, but resource utilization efficiency and elasticity are reduced

Engineering Contradiction:
Improveresource utilization efficiencyVSAvoidnetwork architecture complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent makes the network architecture universal by enabling a single logical IP subnet to span multiple independent layer 2 subnets. This allows the network to function both as a traditional simple network for basic operations and as a sophisticated multi-subnet network for optimized resource utilization. The mapping table provides multi-functionality by supporting both simple direct addressing and complex cross-subnet routing transparently.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS12568024B2System and method for a single logical IP subnet across multiple independent layer 2 (L2) subnets in a high performance computing environment
Publication Date: 2026.03.03 ORACLE INT CORP
  • US12568024B2 patent drawing
  • US12568024B2 patent drawing
  • US12568024B2 patent drawing

AI summary

Systems and methods for supporting a single logical IP subnet across multiple independent layer 2 subnets in a high performance computing environment. A method can provide, at a computer including one or more microprocessors, a logical device, the logical device being addressed by a layer 3 address, wherein the logical device comprises a plurality of network adapters, each of the network adapters comprising a physical port, and a plurality of switches. The method can arrange the plurality of switches into a plurality of discrete layer 2 subnets. The method can provide a mapping table at the logical device.