Logical Power Throttling of Instruction Decode Rate
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Solution Overview
Problem
Existing power management methods for processors rely on physically changing voltage and frequency to reduce consumption, which requires extensive redesign and validation, whereas logical throttling can achieve power reduction without altering these parameters.
Innovation Solution
A processor with a logical power throttling unit that receives a power throttling output signal to adjust the number of instructions decoded per cycle, reducing power consumption by either decreasing the number of instructions in a single cycle or increasing the number of cycles between decodings, without changing processor cycle time or supply voltage levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If physical parameters (voltage, frequency) are changed to reduce power consumption, then power consumption is reduced, but extensive redesign and validation are required
Solution Approach 1:
The patent replaces physical throttling mechanisms (voltage/frequency adjustment) with a logical software-based throttling mechanism. The power management module uses firmware or software code to dynamically adjust the number of instructions decoded per cycle, eliminating the need for hardware redesign and physical parameter changes while achieving the same power reduction effect
Solution Approach 2:
The patent changes the operational parameter from physical (voltage, frequency) to logical (instruction decode rate). By modifying the instruction decode rate through software control, the system achieves power management without altering physical characteristics, thus avoiding redesign and validation requirements
2Use of energy by moving object
If physical parameters are changed to reduce power consumption, then power consumption is reduced, but system functionality may be affected
Solution Approach 1:
The patent substitutes physical parameter changes with logical control mechanisms that preserve system functionality. The power management module dynamically adjusts instruction decoding through software, allowing the system to maintain full functional capability while reducing power consumption, unlike physical throttling that may compromise system operation
3Use of energy by moving object
If the number of instructions decoded per cycle is reduced, then power consumption is reduced, but processing speed decreases
Solution Approach 1:
The patent implements dynamic adjustment of the instruction decode rate based on real-time power management requirements. The power management module can flexibly vary the number of instructions decoded per cycle, allowing the system to optimize between power consumption and processing speed depending on operational conditions, rather than using fixed throttling levels
Solution Approach 2:
The patent dynamically changes the instruction decode rate parameter to balance power consumption and processing speed. By adjusting this logical parameter rather than physical parameters, the system can achieve fine-grained control over the trade-off between power usage and performance without compromising system functionality
Data Source
AI summary
A processor includes a device providing a throttling power output signal. The throttling power output signal is used to determine when to logically throttle the power consumed by the processor. At least one core in the processor includes a pipeline having a decode pipe; and a logical power throttling unit coupled to the device to receive the output signal, and coupled to the decode pipe. Following the logical power throttling unit receiving the power throttling output signal satisfying a predetermined criterion, the logical power throttling unit causes the decode pipe to reduce an average number of instructions decoded per processor cycle without physically changing the processor cycle or any processor supply voltages.