Loop Thread Scheduling in Reconfigurable Computing Fabric
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Solution Overview
Problem
Existing computing systems face limitations in performance, energy efficiency, and heat dissipation, particularly in handling compute-intensive tasks like Fast Fourier Transforms and finite impulse response filters, and lack dynamic self-configuration capabilities for diverse applications such as artificial intelligence and 5G technologies.
Innovation Solution
A multi-threaded, coarse-grained configurable computing architecture with dynamic self-scheduling and self-reconfiguration, conditional branching, and backpressure control, utilizing a configuration memory with instruction and instruction index memories to manage thread execution and data dependencies, enabling efficient execution of loop threads and nested loops.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If existing computing systems are used for compute-intensive tasks, then basic computation can be performed, but performance and energy efficiency are insufficient
Solution Approach 1:
The system segments computation into multiple independent threads that can be executed in parallel across different processing elements. Each thread represents a discrete computational unit that can be scheduled and executed independently, enabling efficient utilization of multiple cores while maintaining energy efficiency through selective activation of processing elements based on workload requirements
Solution Approach 2:
The system implements dynamic thread scheduling where the scheduler can adaptively assign threads to processing elements based on current system state, workload characteristics, and energy constraints. The configuration memory and control logic enable runtime reconfiguration of the computational fabric to optimize for either performance or energy efficiency depending on operational requirements
2Productivity
If existing computing systems are used for compute-intensive tasks, then basic computation can be performed, but heat dissipation becomes excessive
Solution Approach 1:
By dividing the computational workload into segmented threads that can be distributed across multiple processing elements, the system avoids concentrating excessive computational load on single cores, thereby distributing heat generation across multiple lower-power elements and improving thermal management
Solution Approach 2:
The system maintains continuous useful computation through efficient thread scheduling and pipeline techniques, ensuring that processing elements remain productively occupied without requiring excessive frequency increases that would generate more heat. The reconfigurable fabric allows seamless thread migration and load balancing to maintain thermal efficiency
3Adaptability or versatility
If a multi-threaded configurable architecture is implemented, then dynamic self-configuration capability is achieved, but device complexity increases
Solution Approach 1:
The system employs a universal reconfigurable fabric where the same hardware resources can be dynamically configured to execute different types of computational kernels (FFT, FIR filtering, graph analytics, machine learning). The configuration memory stores reusable thread descriptors and data path settings that can be applied across diverse workloads, providing adaptability without proportionally increasing physical complexity
Solution Approach 2:
The system implements self-scheduling capability where the embedded scheduler automatically manages thread allocation, configuration loading, and resource allocation without external intervention. The configuration memory autonomously provides the necessary control signals and parameter settings to the reconfigurable fabric based on the current execution context, reducing the need for complex external control logic
Data Source
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AI summary
Representative apparatus, method, and system embodiments are disclosed for configurable computing. A representative system includes an interconnection network; a processor; and a plurality of configurable circuit clusters. Each configurable circuit cluster includes a plurality of configurable circuits arranged in an array; a synchronous network coupled to each configurable circuit of the array; and an asynchronous packet network coupled to each configurable circuit of the array. A representative configurable circuit includes a configurable computation circuit and a configuration memory having a first, instruction memory storing a plurality of data path configuration instructions to configure a data path of the configurable computation circuit; and a second, instruction and instruction index memory storing a plurality of spoke instructions and data path configuration instruction indices for selection of a master synchronous input, a current data path configuration instruction, and a next data path configuration instruction for a next configurable computation circuit.