Looped Wire Interconnects for Enhanced Bonding Strength
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Solution Overview
Problem
Current technologies face limitations in shrinking transistor sizes and increasing computing power due to physical material constraints, prompting the need for innovative interconnect solutions that enhance bonding and thermal management in compact electronics.
Innovation Solution
The development of looped wire interconnects that provide stronger connections and increased bonding surface area by using bent or looped wires with stud balls, allowing for more robust die-to-PCB interconnections and package-on-package assemblies, which can be formed using wirebonding and ultrasonic welding techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If traditional straight wire interconnects are used, then the manufacturing process is simple, but the bonding strength and thermal management are insufficient
Solution Approach 1:
The patent applies curvature by transforming straight wire interconnects into looped configurations. The looped wire interconnects provide increased bonding surface area and stronger mechanical attachment between substrates, directly addressing the insufficient bonding strength while the loop structure itself is the curvature application that resolves the technical contradiction
2Power
If larger subsystems are packaged into one chip, then computing power increases, but the transistor size must be reduced which hits physical material limits
Solution Approach 1:
The patent transitions from planar 2D packaging to 3D vertical stacking by implementing looped wire interconnects that enable package-on-package and die-to-PCB configurations. This dimensional change allows computing power to increase through vertical integration rather than horizontal scaling, avoiding the transistor size reduction that hits physical material limits
3Power
If interconnect distance is reduced to increase computing power, then more processing power fits in smaller packages, but thermal expansion differences cause connection failures
Solution Approach 1:
The patent directly addresses thermal expansion issues by designing looped wire interconnects that accommodate differential thermal expansion between substrates with widely varying coefficients. The loop structure provides mechanical compliance that absorbs thermal stress, preventing connection failures while enabling high processing power density in compact packages
4Power
If more transistors are placed on a device, then computing power increases, but the available space decreases
Solution Approach 1:
The patent enables increased computing power in smaller volumes by implementing vertical 3D stacking architectures using looped wire interconnects. This transitions from 2D lateral expansion to 3D vertical integration, allowing more transistors and subsystems to be packed into reduced footprints through multiple stacked layers rather than spreading out horizontally
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances the reliability and strength of interconnections between components with varying thermal expansion coefficients, reducing failure rates and enabling more efficient packaging of computing power in smaller spaces.
Implementation Method 1
The wire loop interconnects may be attached to the mounting pad by, for example, arc welding, soldering, ultrasonic welding, or the like
Data Source
AI summary
Disclosed herein is a system and method for mounting packages by forming one or more wire loop interconnects, optionally, with a wirebonder, and mounting the interconnects to a mounting pad on a first substrate. A first and second stud ball may each have at least one flat surface be disposed on a single mounting pad, and a wire having a bend region and forming a loop may be disposed between the stud balls. The stud balls may be formed from a deformed mouthing node formed on a wire. The loop may be mounted on a mounting pad on a first substrate and a second substrate may be mounted on the loop via a conductive material such as solder.