Low-Amplitude Clock Signal Data Transfer in Semiconductor Devices
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor systems face challenges in reducing operating electric current on signal buses and ensuring reliable high-speed data transfer, particularly in AI and system-on-chip devices that require large-scale data processing and high-speed data transfer operations.
Innovation Solution
The semiconductor system incorporates a driver circuit and receiver circuit with low-amplitude clock signals and data transmission, utilizing N-type and P-type MOSFETs to reduce signal amplitude and operating electric current, while ensuring data synchronization with rise edges of clock signals, thereby improving data transfer reliability and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional high-amplitude signals are used for data transfer, then signal integrity is maintained, but operating electric current on the signal bus increases
Solution Approach 1:
The patent changes the voltage amplitude parameter of the signal from conventional high amplitude to low amplitude (lower than power supply voltage). This parameter change reduces the operating electric current on the signal bus while maintaining functional operation of the driver and receiver circuits through optimized circuit design adapted to low-voltage operation.
2Productivity
If high-speed data transfer is implemented, then productivity is improved, but data acquisition time variations increase reducing reliability
Solution Approach 1:
The patent uses preliminary action by pre-synchronizing the receiver circuit to the clock signal before data acquisition. The receiver is prepared and timed in advance based on the clock signal edges, ensuring that data is captured at the optimal moment. This preliminary synchronization minimizes timing variations and enhances reliability of high-speed data transfer.
Solution Approach 2:
The patent implements feedback through the clock signal that provides timing information back to the receiver circuit. The clock signal edges serve as feedback cues that synchronize the receiver's data sampling operation, ensuring consistent timing and reducing acquisition time variations across multiple data transfer operations.
3Reliability
If multi-phase clock signals are used for data transfer, then data acquisition reliability is improved, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the data transfer operation into distinct phases synchronized with different clock signal edges (rise edges of first and second clock signals). Each phase handles specific data acquisition tasks, allowing reliable multi-phase operation while managing complexity through structured temporal division rather than requiring complex simultaneous multi-phase circuitry.
Data Source
AI summary
The data transfer has room for improvement of reduction in the operating electric current flowing on the signal bus and correct acquisition of the large amount of data. Each of data, a first clock signal and a second clock signal, a phase of which shifts by a predetermined amount from the first clock signal, has an amplitude that is smaller than an amplitude of a power supply voltage, and each of a semiconductor device and a memory device takes input of data in synchronization with rise edges of first and second clock signals.