Low-Grade Silicon Package for Embedded Passives
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor devices face challenges with parasitic resistances and inductances, thermal performance, and reliability due to mismatched coefficients of thermal expansion and material compatibility issues, particularly in power switching devices like synchronous Buck converters.
Innovation Solution
A semiconductor package structure and fabrication method using low-grade silicon slabs as both carriers and packages, eliminating leadframes, bonding wires, and plastic encapsulations, and integrating passive components, which reduces thermal stresses and parasitic resistances while enhancing thermal conductivity and manufacturing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional composite packages with leadframes and bonding wires are used, then device assembly is straightforward, but parasitic resistances and inductances increase significantly
Solution Approach 1:
The patent merges the package substrate and interconnection structure into a single integrated low-grade silicon slab. The substrate directly provides both mechanical support and electrical interconnections, eliminating the need for separate leadframes and bonding wires. This integration reduces the number of components and interfaces, thereby reducing parasitic resistances and inductances while maintaining ease of manufacture through standardized wafer fabrication processes.
Solution Approach 2:
The patent extracts and removes the leadframe and bonding wire interconnection structures from the conventional package design. By eliminating these separate components and replacing them with direct substrate-based interconnections, the design reduces parasitic elements while simplifying the overall device architecture.
2Adaptability or versatility
If widely different materials (metals, ceramics, plastics) are used in composite packages, then device functionality is achieved, but thermo-mechanical stress and delamination risk increase
Solution Approach 1:
The patent employs homogeneity by using a single material system (low-grade silicon) for the package substrate and interconnections, rather than combining widely different materials like metals, ceramics, and plastics. This uniform material composition ensures matched coefficients of thermal expansion, eliminating thermo-mechanical stress and delamination risks while maintaining full device functionality through the silicon-based platform.
Solution Approach 2:
The patent uses low-grade silicon as a composite material platform that integrates both structural and electrical functions. This single composite material replaces multiple disparate materials, providing both mechanical support and electrical interconnection while ensuring thermal compatibility across all device components.
3Reliability
If plastic encapsulation is used for device packaging, then device protection is provided, but moisture-related degradation and CTE mismatch issues occur
Solution Approach 1:
The patent replaces plastic encapsulation with a low-grade silicon substrate that provides both mechanical protection and electrical functionality. This homogeneous silicon-based approach eliminates the CTE mismatch between plastic and semiconductor components, while the silicon material's inherent properties provide protection against moisture-related degradation.
4Reliability
If low-grade silicon slabs are used for both chip assembly and packaging, then thermal stresses and parasitic resistances are reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent utilizes parameter changes by leveraging the inherent properties of low-grade silicon, which has relaxed purity requirements compared to semiconductor-grade silicon. This allows the use of standard wafer fabrication processes with typical precision levels to achieve the required manufacturing quality, while the low-grade silicon's thermal properties provide stress reduction benefits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution minimizes thermo-mechanical stresses, reduces parasitic resistances and inductances, improves thermal and electrical performance, and enhances reliability by using low-grade silicon slabs for both chip assembly and packaging, thereby addressing the limitations of conventional composite packages.
Implementation Method 1
improves thermal and electrical performance
Implementation Method 2
minimizes thermo-mechanical stresses
Data Source
AI summary
A packaged electronic system comprises a slab (210) of low-grade silicon (l-g-Si) configured as ridges (114) framing a depression of depth (112) including a recessed central area suitable to accommodate semiconductor chips and embedded electrical components, the depth at least equal to the thickness of the chips and the components, the ridge covered by system terminals (209b) connected to attachment pads in the central area; and semiconductor chips (120, 130) having a thickness and terminals on at least one of opposing chip sides, the chips terminals attached to the central area terminals so that the opposite chip side is coplanar with the system terminals on the slab ridge.