Low Impedance Clock Distribution Bus for IC Skew Reduction
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Solution Overview
Problem
As integrated chips (ICs) become faster and larger, distributing a global clock signal with minimal clock skew and power consumption becomes increasingly difficult, leading to performance degradation and larger die sizes due to traditional clock distribution methods.
Innovation Solution
A clock distribution system using a multi-drop differential bus with low impedance receivers, eliminating the need for terminators and inductors, and employing self-biased gates with common mode feedback and duty cycle correction to dynamically control bias currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If a centralized clock source is used to distribute clock signals to functional blocks, then power consumption is reduced and die size is minimized, but clock skew increases and routing complexity increases as clock frequency and number of functional blocks increase
Solution Approach 1:
The patent segments the clock distribution network into multiple hierarchical levels. Instead of a single centralized source distributing to all functional blocks directly, the clock distribution is divided into regional distribution networks with intermediate clock sources that serve local groups of functional blocks. This segmentation reduces the maximum distribution distance and minimizes clock skew while maintaining lower overall power consumption compared to fully distributed PLLs.
2Reliability
If traditional point-to-point clock distribution is used, then each functional block receives dedicated clock signals, but routing area increases and die size becomes larger
Solution Approach 1:
The patent merges multiple clock distribution paths into a shared hierarchical structure. Instead of dedicated point-to-point connections from the centralized clock source to each functional block, multiple functional blocks share common clock distribution paths through intermediate distribution points. This merging significantly reduces the total routing area required while ensuring reliable clock signal delivery to all functional blocks.
3Ease of operation
If high impedance receivers with terminators and inductors are used in daisy-chained distribution, then clock signals can be distributed, but power is wasted on resistive termination and die area increases
Solution Approach 1:
The patent changes the impedance parameter of the clock signal receivers from high impedance (requiring terminators) to low impedance receivers that do not require resistive termination. This parameter change eliminates the power waste associated with resistive terminators while maintaining proper clock signal distribution. The low impedance receivers can directly interface with the clock distribution network without requiring matching terminators or series inductors, reducing both power consumption and die area.
Data Source
AI summary
Systems and methods to distribute clock signals using a common bus. In one embodiment, a clock signal distribution system includes: a bus; a transmitter coupled to the bus to drive a clock signal onto the bus; and one or more receivers coupled to the bus to receive the clock signal, in which the impedance of each receiver is lower than 1000 ohms (or 500 or 200 ohms). In one embodiment, the clock distribution system is on an integrated circuit to distribute the clock on the integrated circuit chip. In one embodiment, the receivers are self-biased; a bias current of the transmitter is a dynamic sum of bias currents of the receivers; and, each of the receivers has a duty cycle correction mechanism. In one embodiment, there is no inductor between the transmitter and the low impedance receiver in the clock distribution system; and the bus has no terminator.