Low-Inductance Capacitor Layout With Wide, Short Leads
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Multilayer ceramic devices, such as capacitors, face increased inductance due to lead wires, which is undesirable in miniaturization and increased functionality trends, particularly in applications like automotive motor start-stop systems where low inductance is crucial.
Innovation Solution
A low inductance component is designed with a multilayer, monolithic device featuring capacitors connected in series between active and ground terminations, with leads having a length-to-width ratio less than 20, and optionally including a discrete varistor for integrated filtering and EMI/ESD protection, reducing overall inductance and parasitic effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If lead wires are used for connection with other electrical components, then the component can be electrically connected, but the self-inductance of the lead wires increases the overall inductance of the component
Solution Approach 1:
The patent changes the geometric parameters of the lead wires, specifically controlling the ratio of length to maximum width to be less than about 20. This parameter optimization reduces the self-inductance of the leads while maintaining their electrical connection function, directly resolving the contradiction between connection capability and inductance generation.
2Volume of moving object
If the component is miniaturized to meet industry trends, then the component size is reduced, but the inductance control becomes more challenging
Solution Approach 1:
The patent applies parameter changes by optimizing the lead geometry (length-to-width ratio < 20) and capacitor configuration (series connection between active terminations) to achieve low inductance performance in a miniaturized component package, simultaneously addressing both miniaturization and inductance control requirements.
Solution Approach 2:
The patent uses a multilayer, monolithic construction with capacitors arranged in series between active terminations, utilizing three-dimensional space efficiently. This dimensional arrangement allows for compact size while controlling the current path and reducing inductance through optimized layer stacking and electrode configuration.
Data Source
AI summary
A low inductance component may include a multilayer, monolithic device including a first active termination, a second active termination, at least one ground termination, and a pair of capacitors connected in series between the first active termination and the second active termination. The lead(s) may be coupled with the first active termination, second active termination, and/or the at least one ground termination. The lead(s) may have respective length(s) and maximum width(s). A ratio of the length(s) to the respective maximum width(s) of the lead(s) may be less than about 20.