Low-k Dielectric Chip Edge Structure for Reliable Singulation
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Solution Overview
Problem
The challenge of ensuring mechanical reliability during the singulation of semiconductor chips, particularly with the introduction of low-k dielectric layers to reduce parasitic capacitance, is the focus of the technical problem addressed by the semiconductor chip design.
Innovation Solution
The semiconductor chip design includes a device layer on a substrate with a low-k dielectric layer surrounded by a higher permittivity dielectric layer, an isolation recess, and a cover dielectric layer that enhances mechanical stability during singulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the low-k dielectric layer is cut using a blade during singulation, then the chip separation is achieved, but the low-k dielectric layer chips and creates defects
Solution Approach 1:
The cover dielectric layer is formed in advance before the dicing process. This preliminary layer serves as a protective sacrificial layer that absorbs the mechanical impact of the blade, enabling clean cutting without chipping the underlying low-k dielectric layer.
Solution Approach 2:
The cover dielectric layer functions as an intermediary layer between the cutting blade and the low-k dielectric layer. It mediates the cutting process by providing a tougher surface for the blade to cut through, thereby achieving smooth edges on the final chip while maintaining productivity.
2Device complexity
If the low-k dielectric layer is exposed during dicing, then the structure is simplified, but the adhesive film is damaged and stacking reliability is reduced
Solution Approach 1:
The cover dielectric layer is formed preliminarily over the low-k dielectric layer and adhesive film before the dicing process. This protective layer prevents the blade from directly contacting and damaging the adhesive film, thereby preserving stacking reliability while maintaining relatively simple structural implementation.
Data Source
AI summary
A semiconductor chip includes a device layer on a substrate, the device layer including a plurality of semiconductor devices; a wiring structure and a lower inter-wiring dielectric layer each on the device layer, the lower inter-wiring dielectric layer surrounding the wiring structure and having a lower permittivity than silicon oxide; an upper inter-wiring dielectric layer arranged on the lower inter-wiring dielectric layer; an isolation recess arranged along an edge of the substrate, the isolation recess formed on side surfaces of the lower and upper inter-wiring dielectric layers and having a bottom surface at a level equal to or lower than that of a bottom surface of the lower inter-wiring dielectric layer; and a cover dielectric layer covering the side surfaces of the lower and upper inter-wiring dielectric layers and the bottom surface of the isolation recess.