Low Latency Functional Node for Parallel Processing Subsystems

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Solution Overview

Problem

Conventional computer systems experience reduced performance due to serialized execution of tasks between the CPU and GPU, particularly in physics-driven graphics systems where serial data dependencies lead to significant waiting times and reduced concurrency.

Innovation Solution

A method for low latency computation is introduced, which involves exposing a low latency functional node within a parallel processing subsystem that shares a common underlying processor resource, allowing for the scheduling of tasks in a low latency command buffer and prioritizing their execution, along with context switching to improve concurrency between the CPU and GPU.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If tasks are scheduled sequentially in a single command buffer for the GPU, then the GPU can be decoupled from CPU execution and avoid starvation, but the CPU and GPU spend significant time waiting for each other due to serialized execution

Engineering Contradiction:
ImproveGPU execution continuityVSAvoidCPU-GPU waiting time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The single command buffer is segmented into multiple command buffers (first command buffer and second command buffer), allowing the CPU to issue tasks to different buffers concurrently. The GPU can switch between buffers, enabling parallel task issuance while maintaining execution continuity and reducing waiting time.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The CPU prepares and issues tasks to the second command buffer in advance while the GPU is executing tasks from the first command buffer. This preliminary action allows the CPU to remain productive without waiting for GPU completion, reducing overall latency.

Inventive Principle:
Principle #10Preliminary action

2Stability of the object's composition

If the CPU waits for GPU completion before issuing next tasks, then task execution order is maintained, but overall system performance is reduced due to serialization

Engineering Contradiction:
ImproveTask execution orderVSAvoidSystem throughput
Core Design Contradiction:
Stability of the object's compositionVSProductivity

Solution Approach 1:

Multiple command buffers are used to segment the task stream. The CPU can issue tasks to buffer 2 while GPU processes buffer 1, maintaining logical task order through buffer management while enabling concurrent execution and improving throughput.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The command buffer acts as an intermediary between CPU and GPU. By using multiple buffers, the system mediates between the CPU's need to maintain execution order and the GPU's capability for parallel processing, allowing both requirements to be satisfied simultaneously.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Speed

If multiple functional nodes are exposed for the same processor resource, then low latency tasks can be prioritized and executed concurrently with other tasks, but the device complexity increases

Engineering Contradiction:
ImproveTask execution speedVSAvoidDriver complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

Multiple functional nodes are exposed for the same underlying processor resource, allowing the system to handle different task types (low latency vs. standard) through a unified resource. This multi-functionality enables concurrent task processing while sharing hardware resources, improving speed without proportionally increasing physical complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

Multiple functional node interfaces are created that map to a single physical processor resource. This copying of interface layers allows the driver to manage multiple task streams concurrently while the underlying hardware remains shared, reducing actual device complexity while improving execution speed.

Inventive Principle:
Principle #26Copying

Data Source

PatentUS8928677B2Low latency concurrent computation
Publication Date: 2015.01.06 NVIDIA CORP
  • US8928677B2 patent drawing
  • US8928677B2 patent drawing
  • US8928677B2 patent drawing

AI summary

One embodiment of the present invention sets forth a technique for performing low latency computation on a parallel processing subsystem. A low latency functional node is exposed to an operating system. The low latency functional node and a generic functional node are configured to target the same underlying processor resource within the parallel processing subsystem. The operating system stores low latency tasks generated by a user application within a low latency command buffer associated with the low latency functional node. The parallel processing subsystem advantageously executes tasks from the low latency command buffer prior to completing execution of tasks in the generic command buffer, thereby reducing completion latency for the low latency tasks.