Low-Pin Scan Chains with Internal Scan-Enable Decoding
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Solution Overview
Problem
Integrated circuits face challenges in managing increased scan data volumes due to complex fault models and multi-site testing requirements, necessitating enhanced scan compression to reduce test time and cost without compromising quality and reliability, especially in safety-critical sectors like automotive electronics.
Innovation Solution
A design for testing (DFT) method and circuit with a low pin count scan and no dedicated scan enable pin, utilizing internal scan enable signal decoding, on-chip comparator circuits, and efficient data encoding to manage scan chains, allowing for flexible scan compression architectures that optimize pin utilization and reduce test time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If scan compression is increased to reduce test data volume and test time, then test cost and time are reduced, but the complexity of managing scan chains and controlling test phases increases
Solution Approach 1:
The scan chain controller generates its own scan enable signal internally based on the phase of operation (load/unload or capture), eliminating the need for an external scan enable pin. The controller automatically transitions between phases using internal counters and state machines, making the system self-regulating and reducing external control complexity
Solution Approach 2:
The scan chain controller integrates multiple functions into a single unit: it manages phase transitions between load/unload and capture modes, generates the scan enable signal, controls data loading and unloading operations, and manages the scan chain operations. This multi-functionality reduces the overall number of components needed
2Ease of operation
If a dedicated scan enable pin is used to control scan chain operations, then control over scan phases is simplified, but the pin count increases
Solution Approach 1:
The scan chain controller generates its own scan enable signal internally based on the phase of operation (load/unload or capture), eliminating the need for an external scan enable pin. The controller automatically transitions between phases using internal counters and state machines, making the system self-regulating and reducing external control complexity
Solution Approach 2:
The scan enable signal generation function is merged with the scan chain controller's internal logic. Instead of being a separate external pin, the scan enable control is integrated into the controller's state machine and counter logic, combining multiple control functions into a single internal mechanism
3Productivity
If multi-site testing is implemented to increase throughput, then testing capacity is improved, but the volume of scan data that must be managed simultaneously increases
Solution Approach 1:
The scan data management is segmented by implementing separate load/unload phases and capture phases for multiple scan chains. Each scan chain can be independently controlled through the phase-locked counters and state machines, allowing parallel testing of multiple sites while managing data volume through systematic phase-based organization
Solution Approach 2:
The system uses periodic phase transitions (load/unload phase followed by capture phase) that are synchronized across multiple scan chains. The phase-locked counters create periodic counting sequences that coordinate data loading, capturing, and verification across multiple test sites, enabling efficient parallel processing of scan data
Data Source
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AI summary
According to an embodiment, a method (800) for testing using scan chains, without an independent scan enable pin, is proposed. The method includes selectively indicating (802) a capture phase and a load/unload phase for the scan chain based on an encoding of a scan enable signal in an expected signal and a masking signal and loading test parameters to the scan chain during the load/unload phase; operating (804 to 808) the scan chain under functional mode during the capture phase; and generating (810, 812) an error signal based on comparing (806) an output of the scan chain during an unload phase with the expected signal, wherein the masking signal is used to mask the output of the scan chain for cycles with invalid results.