Low-Power Low-Frequency Counter With Hardware Fractional Division

The patent replaces the software-based fractional division mechanism with a hardware-based counter system. The hardware counter automatically generates millisecond tick values through dedicated circuitry that divides the 32.768 kHz clock signal, eliminating the need for software computation. This substitution of hardware for software execution directly reduces power consumption while maintaining measurement precision, as the hardware divider operates continuously without requiring processor instruction cycles.

The patent implements a self-service mechanism where the hardware counter automatically performs the conversion from 32.768 kHz clock cycles to millisecond tick values without software intervention. The counter includes dedicated logic that autonomously calculates the fractional division, generates comparison values, and updates the millisecond count. This self-service approach eliminates the power-consuming software conversion loop while maintaining accurate timing, as the system serves itself without external processor involvement.

The patent replaces software-based fractional division with a hardware counter system that automatically generates millisecond tick values. The hardware divider circuit continuously operates in parallel with processor execution, eliminating the need for software instruction cycles dedicated to conversion. This allows the processor to focus on productive tasks while the hardware counter independently maintains accurate timing, thereby improving overall instruction cycle efficiency without sacrificing measurement precision.

The patent implements continuous hardware-based counting that operates uninterrupted regardless of processor activity. The counter continuously divides the 32.768 kHz clock signal and generates millisecond tick values without pause, ensuring that timing information is always current. This continuous hardware action eliminates the intermittent software polling and conversion operations, improving productivity by freeing instruction cycles while maintaining precise timing through unbroken counting operation.

The patent replaces software-based fractional division with a hardware counter system that automatically generates millisecond tick values through dedicated division logic. This hardware implementation performs the conversion operation in parallel with processor execution, eliminating the sequential computation delay inherent in software. The millisecond count accuracy is maintained without computation time penalty because the hardware divider operates continuously and independently, providing real-time conversion results without blocking processor operations.

The patent implements preliminary action by pre-computing and storing the division ratio constants in hardware registers. The counter logic is pre-configured with the appropriate divisor values for converting 32.768 kHz to 1 kHz, eliminating the need for runtime calculation. This preliminary setup allows the counter to operate with minimal computation time during actual counting, as the division operation uses pre-loaded constants rather than performing complex calculations during each update cycle.

The patent implements dynamic operation mode for the counter, allowing it to switch between active updating and suspended states based on processor activity. When the processor enters low-power mode, the counter automatically suspends its updating operation to conserve power. Upon processor wake-up, the counter resumes updating and performs a catch-up operation using the stored suspension duration. This dynamic adaptation maintains timing accuracy when needed while minimizing power consumption during low-activity periods, as the counter only operates when timing updates are actually required.

The patent implements periodic action by having the counter update at specific intervals rather than continuously. The counter is enabled to update only when the processor transitions between active and low-power states, rather than operating continuously. This periodic updating reduces power consumption during low-power modes while maintaining adequate timing accuracy, as the counter synchronizes its operation with processor state transitions rather than running uninterrupted.

The patent implements a universal counter structure that serves multiple functions: it counts 32.768 kHz clock cycles, performs fractional division to generate millisecond ticks, compares current count against target values, and generates interrupt signals. By consolidating these multiple timing functions into a single hardware counter module, the design reduces overall device complexity compared to having separate circuits for each function. The multi-functional counter achieves power efficiency through hardware-based operation while avoiding the complexity of multiple independent timing circuits.

The patent merges the fractional division logic, counting function, and comparison logic into a single integrated counter circuit. Rather than having separate hardware blocks for division, counting, and comparison, the design combines these functions within one counter module that processes the 32.768 kHz input signal and generates all necessary timing outputs. This merging reduces the number of discrete components and interconnections, thereby reducing device complexity while maintaining the power-efficient hardware-based operation for all timing functions.