Low Power Scan Flip-Flop Cell Maintaining Q Output
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Solution Overview
Problem
High power consumption during scan testing of integrated circuits due to simultaneous toggling of flip-flops and combinational logic, exceeding the circuit's power rating, especially as IC chip density and speed increase.
Innovation Solution
A low power scan flip-flop cell design incorporating a multiplexer, master latch, scan slave latch, and data slave latch, which maintains the Q output signal at a predetermined level during scan mode to prevent unnecessary switching of combinational logic, reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Difficulty of detecting and measuring
If scan mode is enabled to perform testing of integrated circuits, then accessibility to internal nodes is improved, but power consumption increases significantly
Solution Approach 1:
The flip-flop is divided into separate latches (master latch, scan slave latch, data slave latch) with independent control mechanisms. This segmentation allows the scan and data latches to operate independently, enabling scan mode functionality while preventing unnecessary toggling of combinational logic, thus reducing power consumption during testing.
Solution Approach 2:
The patent implements dynamic control of the Q output signal through the data slave latch and scan slave latch mechanism. The Q output is maintained at a predetermined level during scan mode through controlled latch operation, allowing the system to adapt its behavior based on operational mode (scan vs. functional) to minimize power consumption while maintaining testing capability.
2Reliability
If all flip-flops and combinational logic are toggling simultaneously during scan testing, then complete scan coverage is achieved, but power consumption exceeds circuit power rating
Solution Approach 1:
The patent extracts the Q output signal from the data slave latch during scan mode operation. By taking out or isolating the Q output, the design prevents it from changing state during scan shifting, thereby eliminating unnecessary switching of combinational logic that would otherwise be triggered by Q signal changes, thus reducing overall power consumption while maintaining scan coverage.
Solution Approach 2:
The patent applies preliminary anti-action by proactively maintaining the Q output at a predetermined level before and during scan mode operation. This preventive measure stops unnecessary combinational logic switching from occurring in the first place, rather than reacting to power consumption issues after they arise, thereby ensuring power consumption remains within circuit ratings while achieving complete scan coverage.
3Productivity
If IC chip density and speed increase, then circuit functionality is improved, but scan shift power problem is exacerbated
Solution Approach 1:
The patent applies local quality by implementing mode-specific behavior at the flip-flop level. The data slave latch and scan slave latch are configured to provide different behaviors based on operational mode: during scan mode, the Q output is maintained at a predetermined level to prevent combinational logic switching, while during functional mode, normal operation occurs. This localized optimization reduces power consumption during scanning without compromising the high-speed functionality of the IC.
Data Source
AI summary
A low power scan flip-flop cell includes a multiplexer, a master latch, a scan slave latch and a data slave latch. The master latch is connected to the multiplexer, and used for generating a first latch signal. The scan slave latch is connected to the master latch, and generates a scan output (SO) signal. The data slave latch is connected to the master latch, and generates a Q output depending on a scan enable (SE) input signal and the first latch signal. The Q output is maintained at a predetermined level during scan mode, which eliminates unnecessary switching of combinational logic connected to the scan flip-flop cell and thus reduces power consumption.